[Bug middle-end/32889] [4.2 Regression] ICE in delete_output_reload, at reload1.c:7926

["danglin at gcc dot gnu dot org" <gcc-bugzilla@gcc.gnu.org>]

------- Comment #10 from danglin at gcc dot gnu dot org  2007-11-11 16:49 -------
This is a regression in reload.

(gdb) p debug_rtx (insn)
(insn 73 78 76 5 (set (mem/c:SI (plus:SI (reg/f:SI 3 %r3)
                (const_int 17888 [0x45e0])) [19 S4 A32])
        (plus:SI (reg/f:SI 3 %r3)
            (const_int 1056 [0x420]))) 114 {addsi3} (nil)
    (expr_list:REG_EQUIV (plus:SI (reg/f:SI 3 %r3)
            (const_int 1056 [0x420]))
        (nil)))

The problem is in the handling of the destination of insn 73.  The
constraints for the addsi3 pattern only accept register operands.
The pseudo in the lreg pass has been replaced by a temp which must
be reloaded.

I looked at pa_secondary_reload.  It simply returns NO_REGS for
(mem/c:SI (plus:SI (reg/f:SI 3 %r3) (const_int 17888 [0x45e0]))).
The frame offset in the temp exceeds that which can be handled
in a simple move.  So, an intermediate registers is needed.


-- 

danglin at gcc dot gnu dot org changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
          Component|target                      |middle-end


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=32889

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