Re: M0 and M3 patches in linaro toolchains
Am 19.08.2013 17:27, schrieb Keith Packard:
> Wookey <wookey@wookware.org> writes:
>
>> The alternative it to simply repack the existing linaro
>> cross-toolchain sources, but them we get to keep doing that for new
>> releases, and we have gratuitous extra copies of gcc sources and
>> corresponding differences between A* and M* toolchains/versions.
>
> I'm working on this process at the moment; I figure that having a stable
> and reliable compiler will provide a good starting point while we sort
> out how to unify the compiler source code bases.
>
> A simple 'diff' from the linaro q2 release from current Debian 4.7
> compiler sources is something over 700k lines at present; dumping that
> into a package doesn't exactly seem like a good idea.
attaching a diff, comparing the two branches at a merge point (r201326), 398 lines.
Matthias
Index: gcc/doc/invoke.texi
===================================================================
--- gcc/doc/invoke.texi (.../gcc-4_8-branch) (revision 201326)
+++ gcc/doc/invoke.texi (.../ARM/embedded-4_8-branch) (revision 202699)
@@ -11264,7 +11264,7 @@
@samp{arm1156t2-s}, @samp{arm1156t2f-s}, @samp{arm1176jz-s}, @samp{arm1176jzf-s},
@samp{cortex-a5}, @samp{cortex-a7}, @samp{cortex-a8}, @samp{cortex-a9},
@samp{cortex-a15}, @samp{cortex-r4}, @samp{cortex-r4f}, @samp{cortex-r5},
-@samp{cortex-m4}, @samp{cortex-m3},
+@samp{cortex-r7}, @samp{cortex-m4}, @samp{cortex-m3},
@samp{cortex-m1},
@samp{cortex-m0},
@samp{cortex-m0plus},
Index: gcc/testsuite/gcc.target/arm/thumb1-far-jump-2.c
===================================================================
--- gcc/testsuite/gcc.target/arm/thumb1-far-jump-2.c (.../gcc-4_8-branch) (revision 0)
+++ gcc/testsuite/gcc.target/arm/thumb1-far-jump-2.c (.../ARM/embedded-4_8-branch) (revision 202699)
@@ -0,0 +1,57 @@
+/* Check for thumb1 far jump. This is the extreme case that far jump
+ * will be used with minimum number of instructions. By passing this case
+ * it means the heuristic of saving lr for far jump meets the most extreme
+ * requirement. */
+/* { dg-options "-Os" } */
+/* { dg-skip-if "" { ! { arm_thumb1 } } } */
+
+volatile register r4 asm("r4");
+void f3(int i)
+{
+#define GO(n) \
+ extern volatile int g_##n; \
+ r4=(int)&g_##n;
+
+#define GO8(n) \
+ GO(n##_0) \
+ GO(n##_1) \
+ GO(n##_2) \
+ GO(n##_3) \
+ GO(n##_4) \
+ GO(n##_5) \
+ GO(n##_6) \
+ GO(n##_7)
+
+#define GO64(n) \
+ GO8(n##_0) \
+ GO8(n##_1) \
+ GO8(n##_2) \
+ GO8(n##_3) \
+ GO8(n##_4) \
+ GO8(n##_5) \
+ GO8(n##_6) \
+ GO8(n##_7) \
+
+#define GO498(n) \
+ GO64(n##_0) \
+ GO64(n##_1) \
+ GO64(n##_2) \
+ GO64(n##_3) \
+ GO64(n##_4) \
+ GO64(n##_5) \
+ GO64(n##_6) \
+ GO8(n##_0) \
+ GO8(n##_1) \
+ GO8(n##_2) \
+ GO8(n##_3) \
+ GO8(n##_4) \
+ GO8(n##_5) \
+ GO(n##_0) \
+ GO(n##_1) \
+
+ if (i) {
+ GO498(0);
+ }
+}
+
+/* { dg-final { scan-assembler "push.*lr" } } */
Index: gcc/testsuite/gcc.target/arm/thumb1-far-jump-1.c
===================================================================
--- gcc/testsuite/gcc.target/arm/thumb1-far-jump-1.c (.../gcc-4_8-branch) (revision 0)
+++ gcc/testsuite/gcc.target/arm/thumb1-far-jump-1.c (.../ARM/embedded-4_8-branch) (revision 202699)
@@ -0,0 +1,34 @@
+/* Check for thumb1 far jump. Shouldn't save lr for small leaf functions
+ * even with a branch in it. */
+/* { dg-options "-Os" } */
+/* { dg-skip-if "" { ! { arm_thumb1 } } } */
+
+void f()
+{
+ for (;;);
+}
+
+volatile int g;
+void f2(int i)
+{
+ if (i) g=0;
+}
+
+void f3(int i)
+{
+ if (i) {
+ g=0;
+ g=1;
+ g=2;
+ g=3;
+ g=4;
+ g=5;
+ g=6;
+ g=7;
+ g=8;
+ g=9;
+ }
+}
+
+/* { dg-final { scan-assembler-not "push.*lr" } } */
+
Index: gcc/testsuite/ChangeLog.arm
===================================================================
--- gcc/testsuite/ChangeLog.arm (.../gcc-4_8-branch) (revision 0)
+++ gcc/testsuite/ChangeLog.arm (.../ARM/embedded-4_8-branch) (revision 202699)
@@ -0,0 +1,7 @@
+2013-08-05 Terry Guo <terry.guo@arm.com>
+
+ Backport from mainline r197956
+ 2013-04-15 Joey Ye <joey.ye@arm.com>
+
+ * gcc.target/arm/thumb1-far-jump-1.c: New test.
+ * gcc.target/arm/thumb1-far-jump-2.c: New test.
Index: gcc/configure.ac
===================================================================
--- gcc/configure.ac (.../gcc-4_8-branch) (revision 201326)
+++ gcc/configure.ac (.../ARM/embedded-4_8-branch) (revision 202699)
@@ -839,9 +839,10 @@
[enable_languages=c])
AC_ARG_WITH(multilib-list,
-[AS_HELP_STRING([--with-multilib-list], [select multilibs (SH and x86-64 only)])],
+[AS_HELP_STRING([--with-multilib-list], [select multilibs (ARM, SH and x86-64 only)])],
:,
with_multilib_list=default)
+AC_SUBST(with_multilib_list)
# -------------------------
# Checks for other programs
Index: gcc/ChangeLog.arm
===================================================================
--- gcc/ChangeLog.arm (.../gcc-4_8-branch) (revision 0)
+++ gcc/ChangeLog.arm (.../ARM/embedded-4_8-branch) (revision 202699)
@@ -0,0 +1,32 @@
+2013-08-29 Zhenqiang Chen <zhenqiang.chen@arm.com>
+
+ * config/arm/arm.c (arm_option_override): Disable loop2_invariant
+ pass when optimize_size and ira-loop-pressure is not enabled.
+
+2013-08-05 Terry Guo <terry.guo@arm.com>
+
+ Backport from mainline r197956
+ 2013-04-15 Joey Ye <joey.ye@arm.com>
+
+ * config/arm/arm.c (thumb1_final_prescan_insn): Assert lr save
+ for real far jump.
+ (thumb_far_jump_used_p): Count instruction size and set
+ far_jump_used.
+
+2013-08-05 Terry Guo <terry.guo@arm.com>
+
+ Backport from mainline r197153
+ 2013-03-27 Terry Guo <terry.guo@arm.com>
+
+ * config/arm/arm-cores.def: Added core cortex-r7.
+ * config/arm/arm-tune.md: Regenerated.
+ * config/arm/arm-tables.opt: Regenerated.
+ * doc/invoke.texi: Added entry for core cortex-r7.
+
+2013-07-24 Terry Guo <terry.guo@arm.com>
+
+ * configure.ac (with_multilib_list): Export its value.
+ * Makefile.in (with_multilib_list): Import it from configure files.
+ * configure: Regenerated.
+ * config/arm/t-mlibs: New files to define multilibs.
+ * config.gcc: Use above multilib fragment.
Index: gcc/config.gcc
===================================================================
--- gcc/config.gcc (.../gcc-4_8-branch) (revision 201326)
+++ gcc/config.gcc (.../ARM/embedded-4_8-branch) (revision 202699)
@@ -917,7 +917,7 @@
case ${target} in
arm*-*-eabi*)
tm_file="$tm_file newlib-stdint.h"
- tmake_file="${tmake_file} arm/t-bpabi"
+ tmake_file="${tmake_file} arm/t-bpabi arm/t-mlibs"
use_gcc_stdint=wrap
;;
arm*-*-rtems*)
Index: gcc/Makefile.in
===================================================================
--- gcc/Makefile.in (.../gcc-4_8-branch) (revision 201326)
+++ gcc/Makefile.in (.../ARM/embedded-4_8-branch) (revision 202699)
@@ -526,6 +526,7 @@
lang_specs_files=@lang_specs_files@
lang_tree_files=@lang_tree_files@
target_cpu_default=@target_cpu_default@
+with_multilib_list=@with_multilib_list@
OBJC_BOEHM_GC=@objc_boehm_gc@
extra_modes_file=@extra_modes_file@
extra_opt_files=@extra_opt_files@
Index: gcc/config/arm/arm-tables.opt
===================================================================
--- gcc/config/arm/arm-tables.opt (.../gcc-4_8-branch) (revision 201326)
+++ gcc/config/arm/arm-tables.opt (.../ARM/embedded-4_8-branch) (revision 202699)
@@ -259,6 +259,9 @@
Enum(processor_type) String(cortex-r5) Value(cortexr5)
EnumValue
+Enum(processor_type) String(cortex-r7) Value(cortexr7)
+
+EnumValue
Enum(processor_type) String(cortex-m4) Value(cortexm4)
EnumValue
Index: gcc/config/arm/arm.c
===================================================================
--- gcc/config/arm/arm.c (.../gcc-4_8-branch) (revision 201326)
+++ gcc/config/arm/arm.c (.../ARM/embedded-4_8-branch) (revision 202699)
@@ -2134,6 +2134,13 @@
global_options.x_param_values,
global_options_set.x_param_values);
+ /* Do not move invariants out of loops since it tends to increase register
+ pressure. The heuristic to estimate register pressure does not fit for
+ ARM. -fira-loop-pressure tends to get more precise estimation. But it
+ still need more tuning. */
+ if (optimize_function_for_size_p (cfun) && !flag_ira_loop_pressure)
+ flag_move_loop_invariants = 0;
+
/* Register global variables with the garbage collector. */
arm_add_gc_roots ();
}
@@ -22577,6 +22584,11 @@
else if (conds != CONDS_NOCOND)
cfun->machine->thumb1_cc_insn = NULL_RTX;
}
+
+ /* Check if unexpected far jump is used. */
+ if (cfun->machine->lr_save_eliminated
+ && get_attr_far_jump (insn) == FAR_JUMP_YES)
+ internal_error("Unexpected thumb1 far jump");
}
int
@@ -22602,6 +22614,8 @@
thumb_far_jump_used_p (void)
{
rtx insn;
+ bool far_jump = false;
+ unsigned int func_size = 0;
/* This test is only important for leaf functions. */
/* assert (!leaf_function_p ()); */
@@ -22657,6 +22671,26 @@
&& get_attr_far_jump (insn) == FAR_JUMP_YES
)
{
+ far_jump = true;
+ }
+ func_size += get_attr_length (insn);
+ }
+
+ /* Attribute far_jump will always be true for thumb1 before
+ shorten_branch pass. So checking far_jump attribute before
+ shorten_branch isn't much useful.
+
+ Following heuristic tries to estimate more accruately if a far jump
+ may finally be used. The heuristic is very conservative as there is
+ no chance to roll-back the decision of not to use far jump.
+
+ Thumb1 long branch offset is -2048 to 2046. The worst case is each
+ 2-byte insn is assiociated with a 4 byte constant pool. Using
+ function size 2048/3 as the threshold is conservative enough. */
+ if (far_jump)
+ {
+ if ((func_size * 3) >= 2048)
+ {
/* Record the fact that we have decided that
the function does use far jumps. */
cfun->machine->far_jump_used = 1;
Index: gcc/config/arm/arm-cores.def
===================================================================
--- gcc/config/arm/arm-cores.def (.../gcc-4_8-branch) (revision 201326)
+++ gcc/config/arm/arm-cores.def (.../ARM/embedded-4_8-branch) (revision 202699)
@@ -132,6 +132,7 @@
ARM_CORE("cortex-r4", cortexr4, 7R, FL_LDSCHED, cortex)
ARM_CORE("cortex-r4f", cortexr4f, 7R, FL_LDSCHED, cortex)
ARM_CORE("cortex-r5", cortexr5, 7R, FL_LDSCHED | FL_ARM_DIV, cortex)
+ARM_CORE("cortex-r7", cortexr7, 7R, FL_LDSCHED | FL_ARM_DIV, cortex)
ARM_CORE("cortex-m4", cortexm4, 7EM, FL_LDSCHED, cortex)
ARM_CORE("cortex-m3", cortexm3, 7M, FL_LDSCHED, cortex)
ARM_CORE("cortex-m1", cortexm1, 6M, FL_LDSCHED, v6m)
Index: gcc/config/arm/arm-tune.md
===================================================================
--- gcc/config/arm/arm-tune.md (.../gcc-4_8-branch) (revision 201326)
+++ gcc/config/arm/arm-tune.md (.../ARM/embedded-4_8-branch) (revision 202699)
@@ -1,5 +1,5 @@
;; -*- buffer-read-only: t -*-
;; Generated automatically by gentune.sh from arm-cores.def
(define_attr "tune"
- "arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,fa526,fa626,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,iwmmxt2,fa606te,fa626te,fmp626,fa726te,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,arm1156t2fs,genericv7a,cortexa5,cortexa7,cortexa8,cortexa9,cortexa15,cortexr4,cortexr4f,cortexr5,cortexm4,cortexm3,cortexm1,cortexm0,cortexm0plus,marvell_pj4"
+ "arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,fa526,fa626,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,iwmmxt2,fa606te,fa626te,fmp626,fa726te,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,arm1156t2fs,genericv7a,cortexa5,cortexa7,cortexa8,cortexa9,cortexa15,cortexr4,cortexr4f,cortexr5,cortexr7,cortexm4,cortexm3,cortexm1,cortexm0,cortexm0plus,marvell_pj4"
(const (symbol_ref "((enum attr_tune) arm_tune)")))
Index: gcc/config/arm/t-mlibs
===================================================================
--- gcc/config/arm/t-mlibs (.../gcc-4_8-branch) (revision 0)
+++ gcc/config/arm/t-mlibs (.../ARM/embedded-4_8-branch) (revision 202699)
@@ -0,0 +1,86 @@
+# A set of predefined MULTILIB which can be used for different ARM targets.
+# Via the configure option --with-multilib-list, user can customize the
+# final MULTILIB implementation.
+
+comma := ,
+space :=
+space +=
+
+MULTILIB_OPTIONS = mthumb/marm
+MULTILIB_DIRNAMES = thumb arm
+MULTILIB_OPTIONS += march=armv6s-m/march=armv7-m/march=armv7e-m/march=armv7
+MULTILIB_DIRNAMES += armv6-m armv7-m armv7e-m armv7-ar
+MULTILIB_OPTIONS += mfloat-abi=softfp/mfloat-abi=hard
+MULTILIB_DIRNAMES += softfp fpu
+MULTILIB_OPTIONS += mfpu=fpv4-sp-d16/mfpu=vfpv3-d16
+MULTILIB_DIRNAMES += fpv4-sp-d16 vfpv3-d16
+
+MULTILIB_MATCHES = march?armv6s-m=mcpu?cortex-m0
+MULTILIB_MATCHES += march?armv6s-m=mcpu?cortex-m0plus
+MULTILIB_MATCHES += march?armv6s-m=mcpu?cortex-m1
+MULTILIB_MATCHES += march?armv6s-m=march?armv6-m
+MULTILIB_MATCHES += march?armv7-m=mcpu?cortex-m3
+MULTILIB_MATCHES += march?armv7e-m=mcpu?cortex-m4
+MULTILIB_MATCHES += march?armv7=march?armv7-r
+MULTILIB_MATCHES += march?armv7=march?armv7-a
+MULTILIB_MATCHES += march?armv7=mcpu?cortex-r4
+MULTILIB_MATCHES += march?armv7=mcpu?cortex-r4f
+MULTILIB_MATCHES += march?armv7=mcpu?cortex-r5
+MULTILIB_MATCHES += march?armv7=mcpu?cortex-r7
+MULTILIB_MATCHES += march?armv7=mcpu?cortex-a5
+MULTILIB_MATCHES += march?armv7=mcpu?cortex-a7
+MULTILIB_MATCHES += march?armv7=mcpu?cortex-a8
+MULTILIB_MATCHES += march?armv7=mcpu?cortex-a9
+MULTILIB_MATCHES += march?armv7=mcpu?cortex-a15
+MULTILIB_MATCHES += mfpu?vfpv3-d16=mfpu?vfpv3
+MULTILIB_MATCHES += mfpu?vfpv3-d16=mfpu?vfpv3-fp16
+MULTILIB_MATCHES += mfpu?vfpv3-d16=mfpu?vfpv3-d16-fp16
+MULTILIB_MATCHES += mfpu?vfpv3-d16=mfpu?vfpv3xd
+MULTILIB_MATCHES += mfpu?vfpv3-d16=mfpu?vfpv3xd-fp16
+MULTILIB_MATCHES += mfpu?vfpv3-d16=mfpu?vfpv4
+MULTILIB_MATCHES += mfpu?vfpv3-d16=mfpu?vfpv4-d16
+MULTILIB_MATCHES += mfpu?vfpv3-d16=mfpu?neon
+MULTILIB_MATCHES += mfpu?vfpv3-d16=mfpu?neon-fp16
+MULTILIB_MATCHES += mfpu?vfpv3-d16=mfpu?neon-vfpv4
+
+MULTILIB_EXCEPTIONS =
+MULTILIB_REUSE =
+
+MULTILIB_REQUIRED = mthumb
+MULTILIB_REQUIRED += marm
+MULTILIB_REQUIRED += mfloat-abi=hard
+
+MULTILIB_OSDIRNAMES = mthumb=!thumb
+MULTILIB_OSDIRNAMES += marm=!arm
+MULTILIB_OSDIRNAMES += mfloat-abi.hard=!fpu
+
+ifneq (,$(findstring armv6-m,$(subst $(comma),$(space),$(with_multilib_list))))
+MULTILIB_REQUIRED += mthumb/march=armv6s-m
+MULTILIB_OSDIRNAMES += mthumb/march.armv6s-m=!armv6-m
+endif
+
+ifneq (,$(findstring armv7-m,$(subst $(comma),$(space),$(with_multilib_list))))
+MULTILIB_REQUIRED += mthumb/march=armv7-m
+MULTILIB_OSDIRNAMES += mthumb/march.armv7-m=!armv7-m
+endif
+
+ifneq (,$(findstring armv7e-m,$(subst $(comma),$(space),$(with_multilib_list))))
+MULTILIB_REQUIRED += mthumb/march=armv7e-m
+MULTILIB_REQUIRED += mthumb/march=armv7e-m/mfloat-abi=softfp/mfpu=fpv4-sp-d16
+MULTILIB_REQUIRED += mthumb/march=armv7e-m/mfloat-abi=hard/mfpu=fpv4-sp-d16
+MULTILIB_OSDIRNAMES += mthumb/march.armv7e-m=!armv7e-m
+MULTILIB_OSDIRNAMES += mthumb/march.armv7e-m/mfloat-abi.hard/mfpu.fpv4-sp-d16=!armv7e-m/fpu
+MULTILIB_OSDIRNAMES += mthumb/march.armv7e-m/mfloat-abi.softfp/mfpu.fpv4-sp-d16=!armv7e-m/softfp
+endif
+
+ifneq (,$(filter armv7 armv7-r armv7-a,$(subst $(comma),$(space),$(with_multilib_list))))
+MULTILIB_REQUIRED += mthumb/march=armv7
+MULTILIB_REQUIRED += mthumb/march=armv7/mfloat-abi=softfp/mfpu=vfpv3-d16
+MULTILIB_REQUIRED += mthumb/march=armv7/mfloat-abi=hard/mfpu=vfpv3-d16
+MULTILIB_OSDIRNAMES += mthumb/march.armv7=!armv7-ar/thumb
+MULTILIB_OSDIRNAMES += mthumb/march.armv7/mfloat-abi.hard/mfpu.vfpv3-d16=!armv7-ar/thumb/fpu
+MULTILIB_OSDIRNAMES += mthumb/march.armv7/mfloat-abi.softfp/mfpu.vfpv3-d16=!armv7-ar/thumb/softfp
+MULTILIB_REUSE += mthumb/march.armv7=marm/march.armv7
+MULTILIB_REUSE += mthumb/march.armv7/mfloat-abi.softfp/mfpu.vfpv3-d16=marm/march.armv7/mfloat-abi.softfp/mfpu.vfpv3-d16
+MULTILIB_REUSE += mthumb/march.armv7/mfloat-abi.hard/mfpu.vfpv3-d16=marm/march.armv7/mfloat-abi.hard/mfpu.vfpv3-d16
+endif
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