Bug#1003315: ITP: yosys-plugin-ghdl -- VHDL to RTL synthesis plugin using GHDL

[Daniel Gröber <dxld@darkboxed.org>]

Package: wnpp
Severity: wishlist
Owner: Daniel Gröber <dxld@darkboxed.org>
X-Debbugs-Cc: debian-devel@lists.debian.org, dxld@darkboxed.org

* Package name    : yosys-plugin-ghdl
  Version         : 0.0~git20211127.09a32cd
  Upstream Author : Tristan Gingold <tgingold@free.fr>
* URL             : https://github.com/ghdl/ghdl-yosys-plugin/
* License         : GPLv3+
  Programming Lang: C++
  Description     : VHDL to RTL synthesis plugin using GHDL

This yosys plugin allows running RTL synthesis from VHDL source code
instead of yosys' native Verilog.

This allows a full synthesis flow from VHDL to hardware for FPGAs where
the GHDL compiler is used to analyse the VHDL sources and yosys is used to
perform the convertion to netlist format with only free software tools
already in Debian (together with yosys and nextpnr/arachne-pnr).

--Daniel