Bug#761365: ITP: yosys -- A framework for Verilog RTL synthesis

[ruben.undheim@gmail.com]

Package: wnpp
Severity: wishlist
Owner: ruben.undheim@gmail.com


* Package name    : yosys
  Version         : 0.3.0+20140904git01ef34c
  Upstream Author : Clifford Wolf <clifford@clifford.at>
* URL             : http://www.clifford.at/yosys/
* License         : ISC License
  Programming Lang: C++
  Description     : A framework for Verilog RTL synthesis

Yosys is a framework for Verilog RTL synthesis. It currently
has extensive Verilog-2005 support and provides a basic set
of synthesis algorithms for various application domains.

Yosys can be adapted to perform any synthesis job by combining
the existing passes (algorithms) using synthesis scripts and
adding additional passes as needed by extending the yosys C++
code base.

Yosys is free software licensed under the ISC license (a GPL
compatible license that is similar in terms to the MIT license
or the 2-clause BSD license).