Bug#301410: ITP: confluence -- language for synchronous reactive hardware system design
Owner: "Wesley J. Landaker" <firstname.lastname@example.org>
* Package name : confluence
Version : 0.10.4
Upstream Author : Tom Hawkins <email@example.com>
* URL : http://www.confluent.org/
* License : GPL
Description : language for synchronous reactive hardware system design
>From the upstream website <http://www.confluent.org>:
A Confluence program can generate digital logic for an FPGA or ASIC
platform, or C code for hard real-time software.
Confluence combines the component-based methodologies of Verilog and
VHDL with the expressiveness of higher order functional programming.
In comparison to Verilog, VHDL, and C, systems designed in Confluence
result in 2X to 10X code reduction, making the source easier to manage
and reuse. And because Confluence relies on a correct-by-construction
compiler, bugs are reduced--some are prevented altogether--thus
reducing the overall verification effort.
Essentially it's a high-level HDL that can generate VHDL, Verilog, JHDL,
C, etc, from a functional-style description. Quite a few open hardware
cores are written using this language, and it's growing in popularity in
industry as well.