Accepted intel-microcode 3.20170511.1 (amd64 i386 source) into unstable
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA512
Format: 1.8
Date: Mon, 15 May 2017 15:12:25 -0300
Source: intel-microcode
Binary: intel-microcode
Architecture: amd64 i386 source
Version: 3.20170511.1
Distribution: unstable
Urgency: medium
Maintainer: Henrique de Moraes Holschuh <hmh@debian.org>
Changed-By: Henrique de Moraes Holschuh <hmh@debian.org>
Closes: 862606
Description:
intel-microcode - Processor microcode firmware for Intel CPUs
Changes:
intel-microcode (3.20170511.1) unstable; urgency=medium
.
* New upstream microcode datafile 20170511
+ Updated Microcodes:
sig 0x000306c3, pf_mask 0x32, 2017-01-27, rev 0x0022, size 22528
sig 0x000306d4, pf_mask 0xc0, 2017-01-27, rev 0x0025, size 17408
sig 0x000306f2, pf_mask 0x6f, 2017-01-30, rev 0x003a, size 32768
sig 0x000306f4, pf_mask 0x80, 2017-01-30, rev 0x000f, size 16384
sig 0x00040651, pf_mask 0x72, 2017-01-27, rev 0x0020, size 20480
sig 0x00040661, pf_mask 0x32, 2017-01-27, rev 0x0017, size 24576
sig 0x00040671, pf_mask 0x22, 2017-01-27, rev 0x0017, size 11264
sig 0x000406e3, pf_mask 0xc0, 2017-04-09, rev 0x00ba, size 98304
sig 0x000406f1, pf_mask 0xef, 2017-03-01, rev 0xb000021, size 26624
sig 0x000506e3, pf_mask 0x36, 2017-04-09, rev 0x00ba, size 98304
+ This release fixes undisclosed errata on the desktop, mobile and
server processor models from the Haswell, Broadwell, and Skylake
families, including even the high-end multi-socket server Xeons
+ Likely fix the TSC-Deadline LAPIC errata (BDF89, SKL142 and
similar) on several processor families
+ Fix erratum BDF90 on Xeon E7v4, E5v4(?) (closes: #862606)
+ Likely fix serious or critical Skylake errata: SKL138/144,
SKL137/145, SLK149
* Likely fix nightmare-level Skylake erratum SKL150. Fortunately,
either this erratum is very-low-hitting, or gcc/clang/icc/msvc
won't usually issue the affected opcode pattern and it ends up
being rare.
SKL150 - Short loops using both the AH/BH/CH/DH registers and
the corresponding wide register *may* result in unpredictable
system behavior. Requires both logical processors of the same
core (i.e. sibling hyperthreads) to be active to trigger, as
well as a "complex set of micro-architectural conditions"
* source: remove unneeded intel-ucode/ directory
Since release 20170511, upstream ships the microcodes both in .dat
format, and as Linux-style split /lib/firmware/intel-ucode files.
It is simpler to just use the .dat format file for now, so remove
the intel-ucode/ directory. Note: before removal, it was verified
that there were no discrepancies between the two microcode sets
(.dat and intel-ucode/)
* source: remove superseded upstream data file: 20161104
Checksums-Sha1:
9eb22c726c6dc2f91fd8ac1fcb05ce4da85afbfe 1783 intel-microcode_3.20170511.1.dsc
3f4897a172953ddfe9c795eeab3a61b1437911aa 1167628 intel-microcode_3.20170511.1.tar.xz
517c226b3c9fd40d8c55d60311a3a5a46c6b0d1c 4564 intel-microcode_3.20170511.1_amd64.buildinfo
d6f492faabfd0e6290d0cfbe39220613fa97f563 701056 intel-microcode_3.20170511.1_amd64.deb
07b73d565f44198d1e886c5265e2a938f701f597 4251 intel-microcode_3.20170511.1_i386.buildinfo
421e8055cc8af12ba66bc2c5737b3eeea18dbe2f 842094 intel-microcode_3.20170511.1_i386.deb
Checksums-Sha256:
349e63665336dea3eb12e3362db7a2e76a1c4529edc8fbe61fbf62a82f87abc2 1783 intel-microcode_3.20170511.1.dsc
09705f7c52c1b9dcb017dac2d9fc77e28c764fc520c9e55739952fff8795458a 1167628 intel-microcode_3.20170511.1.tar.xz
527a2d698293b66ec9b7da64b94984acc611bde712fb0f73646640173b6a2a7f 4564 intel-microcode_3.20170511.1_amd64.buildinfo
128baacadcc684130dc794714490948fbbbf9047a2399a22080ebc872be12a6f 701056 intel-microcode_3.20170511.1_amd64.deb
e9410ddecc6e27e5c5b283d75401540d01d333ab6fdf59050387a246abb5ae9e 4251 intel-microcode_3.20170511.1_i386.buildinfo
a68eaecbcf56af0f124768c7c37ab7977f51262c549baa49a7ad1946a1928210 842094 intel-microcode_3.20170511.1_i386.deb
Files:
ef62df27e4cad10c016df85c5dacac95 1783 non-free/admin standard intel-microcode_3.20170511.1.dsc
8f218818df62040a608a1bd2886c4413 1167628 non-free/admin standard intel-microcode_3.20170511.1.tar.xz
a649d63fce50e6a914ea41dc70bd6a03 4564 non-free/admin standard intel-microcode_3.20170511.1_amd64.buildinfo
1fcf71e032b7de760aec79d5df2e3982 701056 non-free/admin standard intel-microcode_3.20170511.1_amd64.deb
f2a95f15e220d30d3de3964006e2d6a6 4251 non-free/admin standard intel-microcode_3.20170511.1_i386.buildinfo
4176863ef1ad3a51fa887911b6617de1 842094 non-free/admin standard intel-microcode_3.20170511.1_i386.deb
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAEBCgAGBQJZGfFyAAoJEP4Rv6aLFY6Y/JsQAIrW18t3bWHREMExAK43R+IS
71ovS4etoW5IB3+s86O0liEGyN4PtaMYauaW/Lo+iZA2bGqH3m178hWTk8Zp7V9e
w6Q6iUt6qJ3MxbXWiM4d02OpaHRwLguzOXTdt1HX4E+wl16Z0pP2QwAt9XVEoXNZ
vqvhiuzkfqR09gq/gZ8H7K7Lbx1lZxJp8SEcKHJkOrqYd/53TJlN/CrAtaI2x8XP
DU6fMa2vPVPpsHbMn5j1lHMaFt9bKWxLI6pJC2lwIlcxPXXAV4MgENTynOWQOmXp
cQ/is1YL5TYbjXcnGPCESojPR9s0v2k0YlOXh+vcW8/CWRyBOfE2kF0liqO2BGCr
+D3b2pa4E13/p7xByeoWYxDvCu5+N4kQz6mVwUQQ5vOXuKgJJMY82g83+Vn3pqO2
x3LrIwuJ+rVu+R9zDoaktSCxgLtQ08x99dqT3lni+E2UGeHaofZh5iUODYWw6avF
0g6+3VGpRkk5+O08136jVUgCQjk+WSb8oAVSZA9J1Gqmo7bvgr8FsEt4ClRVHUAY
EoK4c490XVvTFSrM8aYlyKX4WkTp/i0PTiWqmwykU7EFzC5Jg4bPJA5uJ+Xi3kLd
4u19V6i12ZvujlyXX+r9SgV1bRGx6+y8zL4rKWyuSL8yt9iEWW3EE9mfcvBUhP4g
1seFS5ByiLrGRn2YsPCM
=ZyuB
-----END PGP SIGNATURE-----
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