Package: release.debian.org Severity: normal User: release.debian.org@packages.debian.org Usertags: unblock X-Debbugs-Cc: debian-boot@lists.debian.org Please unblock package u-boot This upload is adds support for two more systems; orangepi_zero_plus2 was simply a matter of enabling the target, while the teres_i laptop also required backporting a fix from upstream and adding a configuration and device-tree for the board. The u-boot-install-sunxi64 helper script was modified to auto-detect both of these boards. All changes should be low risk for regressions in other boards. diff -Nru u-boot-2019.01+dfsg/debian/bin/u-boot-install-sunxi64 u-boot-2019.01+dfsg/debian/bin/u-boot-install-sunxi64 --- u-boot-2019.01+dfsg/debian/bin/u-boot-install-sunxi64 2019-04-08 14:01:19.000000000 -0700 +++ u-boot-2019.01+dfsg/debian/bin/u-boot-install-sunxi64 2019-04-19 15:21:52.000000000 -0700 @@ -7,6 +7,8 @@ Pinebook) TARGET="/usr/lib/u-boot/pinebook" ;; Pine64+) TARGET="/usr/lib/u-boot/pine64_plus" ;; "Olimex A64-Olinuxino") TARGET="/usr/lib/u-boot/a64-olinuxino/" ;; + "Olimex A64 Teres-I") TARGET="/usr/lib/u-boot/teres_i/" ;; + "OrangePi Zero Plus2") TARGET="/usr/lib/u-boot/orangepi_zero_plus2/" ;; esac fi diff -Nru u-boot-2019.01+dfsg/debian/changelog u-boot-2019.01+dfsg/debian/changelog --- u-boot-2019.01+dfsg/debian/changelog 2019-04-08 19:47:02.000000000 -0700 +++ u-boot-2019.01+dfsg/debian/changelog 2019-04-19 16:43:08.000000000 -0700 @@ -1,3 +1,15 @@ +u-boot (2019.01+dfsg-5) unstable; urgency=medium + + [ Jonas Smedegaard ] + * Add patch cherry-picked upstream to add i2c initialization for sun50i. + * Add patch by Vasily Khoruzhick to support Olimex Teres-I DIY laptop. + * Enable teres_i target in u-boot-sunxi (Closes: #926040). + + [ Frédéric Danis ] + * Enable orangepi_zero_plus2 target in u-boot-sunxi (Closes: #927224). + + -- Vagrant Cascadian <vagrant@debian.org> Fri, 19 Apr 2019 16:43:08 -0700 + u-boot (2019.01+dfsg-4) unstable; urgency=medium [ Martyn Welch ] diff -Nru u-boot-2019.01+dfsg/debian/patches/series u-boot-2019.01+dfsg/debian/patches/series --- u-boot-2019.01+dfsg/debian/patches/series 2019-04-08 14:01:19.000000000 -0700 +++ u-boot-2019.01+dfsg/debian/patches/series 2019-04-19 15:21:52.000000000 -0700 @@ -26,3 +26,6 @@ # Patches to fix https://bugs.debian.org/923379 dreamplug/ARM-kirkwood-add-spi0-alias-for-dreamplug.patch dreamplug/Commit-ARM-CPU-arm926ejs-Consolidate-cache-routines-.patch + +sunxi/sun50i_i2c_init.patch +sunxi/teres-i.patch diff -Nru u-boot-2019.01+dfsg/debian/patches/sunxi/sun50i_i2c_init.patch u-boot-2019.01+dfsg/debian/patches/sunxi/sun50i_i2c_init.patch --- u-boot-2019.01+dfsg/debian/patches/sunxi/sun50i_i2c_init.patch 1969-12-31 16:00:00.000000000 -0800 +++ u-boot-2019.01+dfsg/debian/patches/sunxi/sun50i_i2c_init.patch 2019-04-19 15:21:52.000000000 -0700 @@ -0,0 +1,71 @@ +Description: add i2c initialization for sun50i + To use TWI0/1/2 the user can select CONFIG_I2C#_ENABLE. + However even the controller is enabled, the mux for the pins + are not set. + . + This patch follows the existing mux method. Since the pads are + different, separate check is added for each i2c. + . + Tested with A64-SOM204 board. +Author: Stefan Mavrodiev <stefan@olimex.com> +Tested-by: Jonas Smedegaard <dr@jones.dk> +Origin: https://git.denx.de/?p=u-boot.git;a=commit;h=da1ae59 +Last-Update: 2019-04-14 +--- +This patch header follows DEP-3: http://dep.debian.net/deps/dep3/ +--- a/arch/arm/include/asm/arch-sunxi/gpio.h ++++ b/arch/arm/include/asm/arch-sunxi/gpio.h +@@ -176,6 +176,7 @@ + + #define SUN5I_GPE_SDC2 3 + #define SUN8I_GPE_TWI2 3 ++#define SUN50I_GPE_TWI2 3 + + #define SUNXI_GPF_SDC0 2 + #define SUNXI_GPF_UART0 4 +@@ -193,8 +194,10 @@ + #define SUN4I_GPH_SDC1 5 + #define SUN6I_GPH_TWI0 2 + #define SUN8I_GPH_TWI0 2 ++#define SUN50I_GPH_TWI0 2 + #define SUN6I_GPH_TWI1 2 + #define SUN8I_GPH_TWI1 2 ++#define SUN50I_GPH_TWI1 2 + #define SUN6I_GPH_TWI2 2 + #define SUN6I_GPH_UART0 2 + #define SUN9I_GPH_UART0 2 +--- a/board/sunxi/board.c ++++ b/board/sunxi/board.c +@@ -98,6 +98,10 @@ + sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0); + sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0); + clock_twi_onoff(0, 1); ++#elif defined(CONFIG_MACH_SUN50I) ++ sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_GPH_TWI0); ++ sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_GPH_TWI0); ++ clock_twi_onoff(0, 1); + #endif + #endif + +@@ -120,6 +124,10 @@ + sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1); + sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1); + clock_twi_onoff(1, 1); ++#elif defined(CONFIG_MACH_SUN50I) ++ sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN50I_GPH_TWI1); ++ sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN50I_GPH_TWI1); ++ clock_twi_onoff(1, 1); + #endif + #endif + +@@ -142,6 +150,10 @@ + sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2); + sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2); + clock_twi_onoff(2, 1); ++#elif defined(CONFIG_MACH_SUN50I) ++ sunxi_gpio_set_cfgpin(SUNXI_GPE(14), SUN50I_GPE_TWI2); ++ sunxi_gpio_set_cfgpin(SUNXI_GPE(15), SUN50I_GPE_TWI2); ++ clock_twi_onoff(2, 1); + #endif + #endif + diff -Nru u-boot-2019.01+dfsg/debian/patches/sunxi/teres-i.patch u-boot-2019.01+dfsg/debian/patches/sunxi/teres-i.patch --- u-boot-2019.01+dfsg/debian/patches/sunxi/teres-i.patch 1969-12-31 16:00:00.000000000 -0800 +++ u-boot-2019.01+dfsg/debian/patches/sunxi/teres-i.patch 2019-04-19 15:21:52.000000000 -0700 @@ -0,0 +1,362 @@ +Description: add support for Olimex Teres-I + * sun50i-a64-teres-i.dts is copied verbatim from Linux 5.0. + * other files are adapted from pinebook files. +Author: Vasily Khoruzhick <anarsoul@gmail.com> +Tested-by: Jonas Smedegaard <dr@jones.dk> +Origin: https://freenode.irclog.whitequark.org/linux-sunxi/2019-04-13#24411386 +Last-Update: 2019-04-14 +--- +This patch header follows DEP-3: http://dep.debian.net/deps/dep3/ +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -415,7 +415,8 @@ + sun50i-a64-pine64-plus.dtb \ + sun50i-a64-pine64.dtb \ + sun50i-a64-pinebook.dtb \ +- sun50i-a64-sopine-baseboard.dtb ++ sun50i-a64-sopine-baseboard.dtb \ ++ sun50i-a64-teres-i.dtb + dtb-$(CONFIG_MACH_SUN9I) += \ + sun9i-a80-optimus.dtb \ + sun9i-a80-cubieboard4.dtb \ +--- /dev/null ++++ b/arch/arm/dts/sun50i-a64-teres-i.dts +@@ -0,0 +1,270 @@ ++/* ++ * Copyright (C) Harald Geyer <harald@ccbib.org> ++ * based on sun50i-a64-olinuxino.dts by Jagan Teki <jteki@openedev.com> ++ * ++ * SPDX-License-Identifier: (GPL-2.0 OR MIT) ++ */ ++ ++/dts-v1/; ++ ++#include "sun50i-a64.dtsi" ++ ++#include <dt-bindings/gpio/gpio.h> ++#include <dt-bindings/input/input.h> ++#include <dt-bindings/pwm/pwm.h> ++ ++/ { ++ model = "Olimex A64 Teres-I"; ++ compatible = "olimex,a64-teres-i", "allwinner,sun50i-a64"; ++ ++ aliases { ++ serial0 = &uart0; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ ++ framebuffer-lcd { ++ eDP25-supply = <®_dldo2>; ++ eDP12-supply = <®_dldo3>; ++ }; ++ }; ++ ++ gpio-keys { ++ compatible = "gpio-keys"; ++ ++ lid-switch { ++ label = "Lid Switch"; ++ gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>; /* PL8 */ ++ linux,input-type = <EV_SW>; ++ linux,code = <SW_LID>; ++ wakeup-source; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ capslock { ++ label = "teres-i:green:capslock"; ++ gpios = <&pio 2 7 GPIO_ACTIVE_HIGH>; /* PC7 */ ++ }; ++ ++ numlock { ++ label = "teres-i:green:numlock"; ++ gpios = <&pio 2 4 GPIO_ACTIVE_HIGH>; /* PC4 */ ++ }; ++ }; ++ ++ reg_usb1_vbus: usb1-vbus { ++ compatible = "regulator-fixed"; ++ regulator-name = "usb1-vbus"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ enable-active-high; ++ gpio = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */ ++ status = "okay"; ++ }; ++ ++ wifi_pwrseq: wifi_pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ ++ }; ++}; ++ ++&ehci1 { ++ status = "okay"; ++}; ++ ++ ++/* The ANX6345 eDP-bridge is on i2c0. There is no linux (mainline) ++ * driver for this chip at the moment, the bootloader initializes it. ++ * However it can be accessed with the i2c-dev driver from user space. ++ */ ++&i2c0 { ++ clock-frequency = <100000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c0_pins>; ++ status = "okay"; ++}; ++ ++&mmc0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc0_pins>; ++ vmmc-supply = <®_dcdc1>; ++ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; ++ disable-wp; ++ bus-width = <4>; ++ status = "okay"; ++}; ++ ++&mmc1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc1_pins>; ++ vmmc-supply = <®_aldo2>; ++ vqmmc-supply = <®_dldo4>; ++ mmc-pwrseq = <&wifi_pwrseq>; ++ bus-width = <4>; ++ non-removable; ++ status = "okay"; ++ ++ rtl8723bs: wifi@1 { ++ reg = <1>; ++ interrupt-parent = <&r_pio>; ++ interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* PL3 */ ++ interrupt-names = "host-wake"; ++ }; ++}; ++ ++&mmc2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc2_pins>; ++ vmmc-supply = <®_dcdc1>; ++ vqmmc-supply = <®_dcdc1>; ++ bus-width = <8>; ++ non-removable; ++ cap-mmc-hw-reset; ++ status = "okay"; ++}; ++ ++&ohci1 { ++ status = "okay"; ++}; ++ ++&r_rsb { ++ status = "okay"; ++ ++ axp803: pmic@3a3 { ++ compatible = "x-powers,axp803"; ++ reg = <0x3a3>; ++ interrupt-parent = <&r_intc>; ++ interrupts = <0 IRQ_TYPE_LEVEL_LOW>; ++ wakeup-source; ++ }; ++}; ++ ++#include "axp803.dtsi" ++ ++®_aldo1 { ++ regulator-always-on; ++ regulator-min-microvolt = <2800000>; ++ regulator-max-microvolt = <2800000>; ++ regulator-name = "vcc-pe"; ++}; ++ ++®_aldo2 { ++ regulator-always-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-pl"; ++}; ++ ++®_aldo3 { ++ regulator-always-on; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-name = "vcc-pll-avcc"; ++}; ++ ++®_dcdc1 { ++ regulator-always-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-3v3"; ++}; ++ ++®_dcdc2 { ++ regulator-always-on; ++ regulator-min-microvolt = <1040000>; ++ regulator-max-microvolt = <1300000>; ++ regulator-name = "vdd-cpux"; ++}; ++ ++/* DCDC3 is polyphased with DCDC2 */ ++ ++®_dcdc5 { ++ regulator-always-on; ++ regulator-min-microvolt = <1500000>; ++ regulator-max-microvolt = <1500000>; ++ regulator-name = "vcc-ddr3"; ++}; ++ ++®_dcdc6 { ++ regulator-always-on; ++ regulator-min-microvolt = <1100000>; ++ regulator-max-microvolt = <1100000>; ++ regulator-name = "vdd-sys"; ++}; ++ ++®_dldo1 { ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-hdmi"; ++}; ++ ++®_dldo2 { ++ regulator-min-microvolt = <2500000>; ++ regulator-max-microvolt = <2500000>; ++ regulator-name = "vcc-pd"; ++}; ++ ++®_dldo3 { ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1200000>; ++ regulator-name = "vdd-edp"; ++}; ++ ++®_dldo4 { ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-wifi-io"; ++}; ++ ++®_eldo1 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "cpvdd"; ++}; ++ ++®_eldo2 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc-dvdd-csi"; ++}; ++ ++®_fldo1 { ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1200000>; ++ regulator-name = "vcc-1v2-hsic"; ++}; ++ ++/* ++ * The A64 chip cannot work without this regulator off, although ++ * it seems to be only driving the AR100 core. ++ * Maybe we don't still know well about CPUs domain. ++ */ ++®_fldo2 { ++ regulator-always-on; ++ regulator-min-microvolt = <1100000>; ++ regulator-max-microvolt = <1100000>; ++ regulator-name = "vdd-cpus"; ++}; ++ ++®_rtc_ldo { ++ regulator-name = "vcc-rtc"; ++}; ++ ++&simplefb_hdmi { ++ vcc-hdmi-supply = <®_dldo1>; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pb_pins>; ++ status = "okay"; ++}; ++ ++&usbphy { ++ usb1_vbus-supply = <®_usb1_vbus>; ++ status = "okay"; ++}; +--- /dev/null ++++ b/configs/teres_i_defconfig +@@ -0,0 +1,21 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_SUNXI=y ++CONFIG_SPL=y ++CONFIG_MACH_SUN50I=y ++CONFIG_DRAM_CLK=552 ++CONFIG_DRAM_ZQ=3881949 ++CONFIG_MMC_SUNXI_SLOT_EXTRA=2 ++CONFIG_I2C0_ENABLE=y ++# CONFIG_CMD_FLASH is not set ++# CONFIG_SPL_DOS_PARTITION is not set ++# CONFIG_SPL_EFI_PARTITION is not set ++CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-teres-i" ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_SUNXI=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y ++# CONFIG_USB_GADGET is not set ++CONFIG_VIDEO_BRIDGE=y ++CONFIG_VIDEO_BRIDGE_ANALOGIX_ANX6345=y +--- /dev/null ++++ b/arch/arm/dts/sun50i-a64-teres-i-u-boot.dtsi +@@ -0,0 +1,41 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (C) 2019 Vasily Khoruzhick <anarsoul@gmail.com> ++ * ++ */ ++ ++#include "sunxi-u-boot.dtsi" ++ ++/ { ++ vdd_bl: regulator@0 { ++ compatible = "regulator-fixed"; ++ regulator-name = "bl-3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */ ++ enable-active-high; ++ }; ++ ++ backlight: backlight { ++ compatible = "pwm-backlight"; ++ pwms = <&pwm 0 50000 0>; ++ brightness-levels = <0 5 10 15 20 30 40 55 70 85 100>; ++ default-brightness-level = <2>; ++ enable-gpios = <&pio 3 23 GPIO_ACTIVE_HIGH>; /* PD23 */ ++ power-supply = <&vdd_bl>; ++ }; ++}; ++ ++/* The ANX6345 eDP-bridge is on i2c */ ++&i2c0 { ++ anx6345: edp-bridge@38 { ++ compatible = "analogix,anx6345"; ++ reg = <0x38>; ++ reset-gpios = <&pio 3 24 GPIO_ACTIVE_LOW>; /* PD24 */ ++ status = "okay"; ++ }; ++}; ++ ++&pwm { ++ status = "okay"; ++}; diff -Nru u-boot-2019.01+dfsg/debian/targets u-boot-2019.01+dfsg/debian/targets --- u-boot-2019.01+dfsg/debian/targets 2019-04-08 14:01:19.000000000 -0700 +++ u-boot-2019.01+dfsg/debian/targets 2019-04-19 15:21:52.000000000 -0700 @@ -200,12 +200,18 @@ # Rodrigo Exterckötter Tjäder <rodrigo@tjader.xyz> arm64 sunxi a64-olinuxino u-boot.bin spl/sunxi-spl.bin u-boot-nodtb.bin arch/arm/dts/sun50i-a64-olinuxino.dtb +# Frederic Danis <frederic.danis@collabora.com> +arm64 sunxi orangepi_zero_plus2 u-boot.bin spl/sunxi-spl.bin u-boot-nodtb.bin arch/arm/dts/sun50i-h5-orangepi-zero-plus2.dtb + # Vagrant Cascadian <vagrant@debian.org> arm64 sunxi pine64_plus u-boot.bin spl/sunxi-spl.bin u-boot-nodtb.bin arch/arm/dts/sun50i-a64-pine64-plus.dtb arch/arm/dts/sun50i-a64-pine64.dtb # Vagrant Cascadian <vagrant@debian.org> arm64 sunxi pinebook u-boot.bin spl/sunxi-spl.bin u-boot-nodtb.bin arch/arm/dts/sun50i-a64-pinebook.dtb +# Jonas Smedegaard <dr@jones.dk> +arm64 sunxi teres_i u-boot.bin spl/sunxi-spl.bin u-boot-nodtb.bin arch/arm/dts/sun50i-a64-teres-i.dtb + # Vagrant Cascadian <vagrant@debian.org> arm64 tegra p2371-2180 u-boot.bin unblock u-boot/2019.01+dfsg-5 Thanks for considering! live well, vagrant
Attachment:
signature.asc
Description: PGP signature