[Date Prev][Date Next] [Thread Prev][Thread Next] [Date Index] [Thread Index]

Accepted intel-microcode 3.20151106.1~bpo8+1 (amd64 i386 source) into jessie-backports, jessie-backports



-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA512

Format: 1.8
Date: Tue, 10 Nov 2015 20:21:31 -0200
Source: intel-microcode
Binary: intel-microcode
Architecture: amd64 i386 source
Version: 3.20151106.1~bpo8+1
Distribution: jessie-backports
Urgency: medium
Maintainer: Henrique de Moraes Holschuh <hmh@debian.org>
Changed-By: Henrique de Moraes Holschuh <hmh@debian.org>
Closes: 777356
Description: 
 intel-microcode - Processor microcode firmware for Intel CPUs
Changes:
 intel-microcode (3.20151106.1~bpo8+1) jessie-backports; urgency=medium
 .
   * Rebuild for jessie-backports (no changes)
 .
 intel-microcode (3.20151106.1) unstable; urgency=medium
 .
   * New upstream microcode data file 20151106
     + New Microcodes:
       sig 0x000306f4, pf mask 0x80, 2015-07-17, rev 0x0009, size 14336
       sig 0x00040671, pf mask 0x22, 2015-08-03, rev 0x0013, size 11264
     + Updated Microcodes:
       sig 0x000306a9, pf mask 0x12, 2015-02-26, rev 0x001c, size 12288
       sig 0x000306c3, pf mask 0x32, 2015-08-13, rev 0x001e, size 21504
       sig 0x000306d4, pf mask 0xc0, 2015-09-11, rev 0x0022, size 16384
       sig 0x000306f2, pf mask 0x6f, 2015-08-10, rev 0x0036, size 30720
       sig 0x00040651, pf mask 0x72, 2015-08-13, rev 0x001d, size 20480
     * This massive Haswell + Broadwell (and related Xeons) update fixes
       several critical errata, including the high-hitting BDD86/BDM101/
       HSM153(?) which triggers an MCE and locks the processor core
       (LP: #1509764)
     * Might fix critical errata BDD51, BDM53 (TSX-related)
   * source: remove superseded upstream data file: 20150121
   * Add support for supplementary microcode bundles:
     + README.source: update and mention supplementary microcode
     + Makefile: support supplementary microcode
       Add support for supplementary microcode bundles, which (unlike .fw
       microcode override files) can be superseded by a higher revision
       microcode from the latest regular microcode bundle.  Also, fix the
       "oldies" target to have its own exclude filter (IUC_OLDIES_EXCLUDE)
   * Add support for x32 arch:
     + README.source: mention x32
     + control,rules: enable building on x32 arch (Closes: #777356)
   * ucode-blacklist: add Broadwell and Haswell-E signatures
     Add a missing signature for Haswell Refresh (Haswell-E) to the "must
     be updated only by the early microcode update driver" list.  There is
     at least one report of one of the Broadwell microcode updates disabling
     TSX-NI, so add them as well just in case
Checksums-Sha1: 
 f9cca0b3b2b98e1d265c836e71e9e4a0fc4b37e9 1802 intel-microcode_3.20151106.1~bpo8+1.dsc
 71013a733492b24415d29b86c5780d066015ddc0 925228 intel-microcode_3.20151106.1~bpo8+1.tar.xz
 18537f975b4d81dbea767e7078bf5d8bb90b7c35 472576 intel-microcode_3.20151106.1~bpo8+1_amd64.deb
 2c8ba560ed04c9ad5b5c42527fc165b5559081e4 613292 intel-microcode_3.20151106.1~bpo8+1_i386.deb
Checksums-Sha256: 
 327e9f51a2584c70ae8c6fc6a4fa8110c2a626dd37d8dab1cf64b347c92a1e87 1802 intel-microcode_3.20151106.1~bpo8+1.dsc
 5740b4bd883782400ddd8f97fa1d7043136ee9beb3adf79fff0486677365535e 925228 intel-microcode_3.20151106.1~bpo8+1.tar.xz
 f4f415967ed020e7dcc8995b028ce74c5a64c239ee165237f65f25dac2950dcc 472576 intel-microcode_3.20151106.1~bpo8+1_amd64.deb
 94af6b7ef4132c197625a9b7a5f9b2709a9153b6b8ec9ecac1c98046d248ee90 613292 intel-microcode_3.20151106.1~bpo8+1_i386.deb
Files: 
 91c9f4837b0e2620cda46d8404555af4 1802 non-free/admin standard intel-microcode_3.20151106.1~bpo8+1.dsc
 84a375807def6abd3907e56a054a8142 925228 non-free/admin standard intel-microcode_3.20151106.1~bpo8+1.tar.xz
 723f1207c6faaf94728abcd88e76a9ae 472576 non-free/admin standard intel-microcode_3.20151106.1~bpo8+1_amd64.deb
 fcbe9adae9a2e339f5286d6eab7bb3b6 613292 non-free/admin standard intel-microcode_3.20151106.1~bpo8+1_i386.deb

-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1

iQIcBAEBCgAGBQJWWed4AAoJEJE3+9PebwqTUbwQAJxLMLgWTiiTN+l0i8vfD68O
aGIKE8qlvVqrhlLuQm5drj45K1rlJ7xXN1qcCwyfthy0IOKqHsQxWYEoD/kbmA/W
wf88PZL2a1UxPhK8m2hpHkg2FnVDMjdwO0GWb5gFoR5bYpZKtB7G3y4MFfcFlLI4
ENh1eTC/iydAXCwpIjH5GMoJpDDdHhkOshaFwo4/CzdW+bZe0ZpfMlnVNRZcXPZ+
zzxvWMULuVq8OeOQWIEpEjyjLgz2kBbzYf4DhnGV+fZ3DhiWA/7NjMTJuB7QBQIa
n9m8SQEGivLvS1dmimgJFZR+k7EH/F7XdPsHacR3HldpIxhHI/qZnbK8OBz7FJgM
4SnhWCZFvEeCmNqep/uMDx8n6gENQyFm/BgC9EoKOG7IR78mT4w66h1gF0gQn47Z
pP2XH4ai1o0luEOs6HgbXnSxbLkKu2uf35dw0XZIHM3PshaG7JssfSIS/7Nzh3KP
m8szGLpX90RGK4YxKBsRZSrr8hZSQ4dljjPtDocUaheU986FiW93nkR5khMLdRXI
xoXk6LtEYrlowH3+0OIQx30R1ZUTmEjDZ8S5x5t46GcWzxVxxaQFTarrCvVYrBJw
AkXfHoVun8jP5trOAeHw9/2tnJjCuJyhT0oRsMmmFgPV9JADHlrPhjYfTiLIfynB
CZL4AZs/mx4/OcV+7/3z
=kLWt
-----END PGP SIGNATURE-----


Reply to: