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Re: Porting linux on ARM926EJ-S based SOC



On Fri, Aug 31, 2007 at 09:20:27PM +0530, Inderpal wrote:
>  
> 
> Hi there,

Hi,

First of all please note that this mailing list is not a general
ARM development list, but a list about ARM on Debian GNU/Linux.

I would suggest you to use the Linux-arm-kernel mailing list instead.

>  
> 
> We are porting GIT linux 2.6.21 on Arm based SOC.
> 
>  
> 
> We created machine type for our custom board in file
> "arch/arm/tools/mach-types".
> 
>  
> 
> We modified all files in base port "arch/arm/mach_xxx" also all header file
> "include/asm/arch-xxx" as per memory map of our board.
> 
>  
> 
> But kernel execution fails after "Uncompressing Linux...  done, booting the
> kernel."
> 
>  
> 
> We checked all serial port initialization and all macros like "ZBSSADDR,
> ZRELADDR, INITRD_PHYS, INITRD_VIRT, and PARAMS_PHYS " with memory map of our
> board.But kernel execution failed.
> 
>  
> 
>  
> 
> I tried to debug "arch/arm/boot/compressed/head.S" 
> 
>  
> 
> I found exection stops after 
> 
>  
> 
> bl      decompress_kernel
> 
> add     r0, r0, #127
> 
> bic     r0, r0, #127            @ align the kernel length
> 
>  
> 
> add     r1, r5, r0              @ end of decompressed kernel
> 
> adr     r2, reloc_start
> 
> ldr     r3, LC1
> 
> add     r3, r2, r3
> 
> ldmia   r2!, {r9 - r14}         @ copy relocation code
> 
> stmia   r1!, {r9 - r14}
> 
> ldmia   r2!, {r9 - r14}
> 
> stmia   r1!, {r9 - r14}
> 
> cmp     r2, r3
> 
> blo     1b
> 
>  
> 
> Execution does proceed after this piece of code.
> 
>  
> 
> Any Pointer will be greatly appreciated
> 

This is most probably a cache problem. The ARM926EJ has a four way
cache, you have to make sure to flush all the cache. The following 
patch may help:

--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -635,6 +635,8 @@
 1:		ldr	r3, [r1], r11		@ s/w flush D cache
 		teq	r1, r2
 		bne	1b
+2:		mrc     p15, 0, r15, c7, c14, 3	@ test,clean,invalidate
+		bne     2b
 
 		mcr	p15, 0, r1, c7, c5, 0	@ flush I cache
 		mcr	p15, 0, r1, c7, c6, 0	@ flush D cache


Cheers,
Aurelien

-- 
  .''`.  Aurelien Jarno	            | GPG: 1024D/F1BCDB73
 : :' :  Debian developer           | Electrical Engineer
 `. `'   aurel32@debian.org         | aurelien@aurel32.net
   `-    people.debian.org/~aurel32 | www.aurel32.net



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