Re: gmp

[Alan Post <alan.post@usa.net>]

On Tue, Aug 31, 1999 at 10:26:38AM +0100, Philip Blundell wrote:
> >I removed the source for 2.95 (which was what I built), so I'm not
> >100% certain that haifa wasn't used.
> 
> See if it supports options like -fsched-interblock and -sched-verbose-N.  If 
> so, it's got Haifa on.  I do have a vague feeling that Debian might have been 
> doing this at one point, and it's a definite no-no for 2.95.x on ARM.

This works:

gcc -O2 -fsched-interblock -fsched-verbose-0 -o test test.c


I assume the presence of these options is bad in itself?

Alan



-fsched-verbose-1 spits out:


;;   ======================================================
;;   -- basic block 0 from 22 to 15 -- before reload
;;   ======================================================


;;	Ready list (t =  1):    10

;;	Ready list (t =  3):    11

;;	Ready list (t =  4):    14

;;	Ready list (t =  5):    15
;;	Ready list (final):  

;;   ==================== scheduling visualization for block 0  
;;   clock     write_blockage                     core                               no-unit 
;;   =====     ==============================     ==============================     ======= 
;;   1         10   r0=`*.LC0'                    10   r0=`*.LC0'                  
;;       .
;;   3         11   r0=call [`printf']            ------------------------------   
;;   4         ------------------------------     ------------------------------     14      
;;   5         ------------------------------     ------------------------------     15      

;;   total time = 5
;;   new basic block head = 22
;;   new basic block end = 15

;; register 0 life extended from 2 to 4
;; register 1 life extended from 0 to 3
;; register 2 life extended from 0 to 3
;; register 3 life extended from 0 to 3
;; register 11 life shortened from 5 to 4
;; register 12 life extended from 0 to 3
;; register 13 life shortened from 5 to 4
;; register 16 life extended from 0 to 3
;; register 17 life extended from 0 to 3
;; register 18 life extended from 0 to 3
;; register 19 life extended from 0 to 3
;; register 25 life shortened from 5 to 4

;; Procedure interblock/speculative motions == 0/0 


;;   ======================================================
;;   -- basic block 0 from 22 to 15 -- after reload
;;   ======================================================


;;	Ready list (t =  1):    10  27

;;	Ready list (t =  2):    10  28

;;	Ready list (t =  3):    30  10

;;	Ready list (t = 13):    10

;;	Ready list (t = 15):    11

;;	Ready list (t = 16):    14

;;	Ready list (t = 17):    15
;;	Ready list (final):  

;;   ==================== scheduling visualization for block 0  
;;   clock     write_buf                          write_blockage                     core                               no-unit 
;;   =====     ==============================     ==============================     ==============================     ======= 
;;   1         ------------------------------     ------------------------------     ------------------------------     27      
;;   2         28   {[--sp]=unspec[fp] 2;use      ------------------------------     28   {[--sp]=unspec[fp] 2;use    
;;   3         28   {[--sp]=unspec[fp] 2;use      ------------------------------     28   {[--sp]=unspec[fp] 2;use      30      
;;       .........
;;   13        ------------------------------     10   r0=`*.LC0'                    10   r0=`*.LC0'                  
;;       .
;;   15        ------------------------------     11   r0=call [`printf']            ------------------------------   
;;   16        ------------------------------     ------------------------------     ------------------------------     14      
;;   17        ------------------------------     ------------------------------     ------------------------------     15      

;;   total time = 17
;;   new basic block head = 22
;;   new basic block end = 15