Re: [buildd] Speedup
> > What's the correct definition of ISA_SEX, given that the adapter is 8 bit
> > only?
>
> If you say adapter, do you mean the bus, or the network adapter itself?
The ROM port to ISA slot adapter.
> It also depends on whether the driver uses anything other than
> in[s]b()/out[s]b(). If it doesn't, ISA_SEX is irrelevant.
It uses word access as well (including string functions).
> If it does, you will need to make the in[s]{w,l}() and out[s]{w,l}()
> functions behave correctly for your bus. What happens if you do a 16 bit
> read/write? What happens if you do a 32 bit read/write?
/* Hardware circuit description (see directory ETHERNEC for schematics)
*
* As there is no reset line on the CP, a resistor and a capacitor are
* used to reset the NE card on power up.
*
* Reading from the NE card is done by a read cycle on the CP at address
* /ROM4 + 512*ISA address as the ISA address lines A0-A4 are connected
* to CP A9-A13. /ROM4 going low will start the ISA read cycle, enable
* the ISA bus buffers of the NE card and start decoding of the ISA IO
* address by the NE card. /ROM4 going high ends the cycle and the
* processor latches the data.
*
* Because the CP is read only writing to the NE card must be done with
* the trick to read from addresses that stand for the data. Dummy reads
* at /ROM3 base address + data*2 + ISA address*512 effect this. You
* might wonder why everything appears to be shifted up one bit. There is
* no CP "A0" address line. There are the signals /UDS and /LDS instead
* typical for the 68000 family. The original design which generated an
* "A0" worked on an ST and an STE but did not on a Falcon.
*
* The falling edge of /ROM3 enables the CP address lines A1-A8 onto the
* data bus and starts the ISA write cycle. The rising edge will end the
* ISA write cycle and the NE latches the data. The processor will also
* see and just read this same data but that is harmless.
*/
D8-15 of the ROM port are connected to D0-7 on the ISA slot. Meaning I
neeed to read a short and shift down to get the correct byte.
Likewise, A9-13 are connected to A0-4, with A1-8 latched to D0-7 to
implement the writes. D8-D15 on the ISA side are not connected at all. So
no short or even long reads or writes at all.
> If your bus doesn't solve it for you, you may need to do 2 or 4
> inb()/outb() calls (in the correct order to get a little-endian result
> short/long) to emulate the "expected" behaviour.
Looks like I need to write a few more raw_io functions then.
> The same goes for the string functions. You basically need to make sure
> normal drivers don't have to be modified to run on your bus.
That's the plan :-)
Michael
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