xserver-xorg-video-intel: Changes to 'upstream-unstable'
.gitignore | 1
README | 23
configure.ac | 11
man/intel.man | 60
src/Makefile.am | 2
src/bios_reader/bios_reader.c | 9
src/ch7017/ch7017.c | 2
src/ch7xxx/ch7xxx.c | 2
src/common.h | 31
src/i2c_vid.h | 130 +
src/i810_driver.c | 19
src/i810_reg.h | 164 +
src/i830.h | 56
src/i830_accel.c | 17
src/i830_bios.c | 59
src/i830_bios.h | 52
src/i830_common.h | 6
src/i830_crt.c | 119 -
src/i830_debug.c | 177 +
src/i830_display.c | 131 +
src/i830_dri.c | 53
src/i830_driver.c | 279 +-
src/i830_dvo.c | 290 ++
src/i830_exa.c | 31
src/i830_lvds.c | 241 +-
src/i830_memory.c | 179 +
src/i830_render.c | 22
src/i830_sdvo.c | 20
src/i830_tv.c | 9
src/i830_video.c | 4622 +++++++++++++++++++++---------------------
src/i830_video.h | 3
src/i830_xaa.c | 6
src/i915_reg.h | 11
src/i915_render.c | 13
src/i915_video.c | 160 -
src/i965_render.c | 87
src/i965_video.c | 16
src/ivch/ivch.c | 211 +
src/ivch/ivch_reg.h | 208 +
src/sil164/sil164.c | 2
src/tfp410/Makefile.am | 16
src/tfp410/tfp410.c | 265 ++
src/tfp410/tfp410.h | 33
src/tfp410/tfp410_module.c | 38
src/tfp410/tfp410_reg.h | 104
45 files changed, 5008 insertions(+), 2982 deletions(-)
New commits:
commit 3c552af65d28fafec1d09484a8914b690b961349
Author: Eric Anholt <eric@anholt.net>
Date: Mon Jul 2 18:33:47 2007 -0700
Update documentation and bump driver version to 2.1.0.
diff --git a/README b/README
index bcb0205..c91c661 100644
--- a/README
+++ b/README
@@ -1,6 +1,6 @@
Information for Intel graphics driver users
Eric Anholt
-2007-04-02
+2007-07-02
This document provides a brief summary of the Intel graphics support provided
by the xf86-video-intel driver. More information can also be found in the
@@ -15,9 +15,14 @@ Supported Hardware:
i845
i852
i855
- i915
- i945
- i965
+ 915G
+ 915GM
+ 945G
+ 945GM/GME
+ 946GZ
+ G965
+ GM/GME965
+ G33/Q33/Q35
Features
- Full support for 8, 15, 16, and 24 bit pixel depths.
@@ -70,6 +75,9 @@ Known Limitations
release.
- Gray output with integrated TV-out and PAL TVs.
- EXA support unstable on i845.
+- Some GM965 systems, such as the Thinkpad T61, probe the TV as being connected
+ even when no output connector is available. This results in the gnome-panel
+ issue noted below.
Common issues not caused by the driver
- Font sizes (DPI) are wrong. Some displays incorrectly report their
@@ -80,7 +88,7 @@ Common issues not caused by the driver
- gnome-panel is located in the middle of the screen. gnome-panel places
itself within head #0's boundaries, which doesn't work well with a second
head covering the same area as head #0 but larger.
-- Older resolution-changing applicationss have poor results in
+- Older resolution-changing applications have poor results in
multihead systems. Previous extensions such as RandR 1.1 exposed only a
single output to client programs, and those requests map poorly to multi-head
systems. Currently, those requests map to just one of the outputs in the
diff --git a/configure.ac b/configure.ac
index a39635e..ec30376 100644
--- a/configure.ac
+++ b/configure.ac
@@ -22,7 +22,7 @@
AC_PREREQ(2.57)
AC_INIT([xf86-video-intel],
- 2.0.0,
+ 2.1.0,
[https://bugs.freedesktop.org/enter_bug.cgi?product=xorg],
xf86-video-intel)
diff --git a/man/intel.man b/man/intel.man
index 8991619..75280a7 100644
--- a/man/intel.man
+++ b/man/intel.man
@@ -24,14 +24,15 @@ the 830M and later.
.SH SUPPORTED HARDWARE
.B intel
supports the i810, i810-DC100, i810e, i815, i830M, 845G, 852GM, 855GM,
-865G, 915G, 915GM, 945G, 945GM, 965G, 965Q, 946GZ and 965GM chipsets.
+865G, 915G, 915GM, 945G, 945GM, 965G, 965Q, 946GZ, 965GM, 945GME,
+G33, Q33, and Q35 chipsets.
.SH CONFIGURATION DETAILS
Please refer to __xconfigfile__(__filemansuffix__) for general configuration
details. This section only covers configuration details specific to this
driver.
.PP
-The Intel 8xx and 9xx families of integrated graphics chipsets has a unified
+The Intel 8xx and 9xx families of integrated graphics chipsets have a unified
memory architecture and uses system memory for video ram. For the i810 and
i815 family of chipset, operating system support for allocating system
memory for video use is required in order to use this driver. For the 830M
@@ -66,12 +67,9 @@ Default: undefined.
.TP
.BI "Option \*qCacheLines\*q \*q" integer \*q
This allows the user to change the amount of graphics memory used for
-2D acceleration and video. Decreasing this amount leaves more for 3D
-textures. Increasing it can improve 2D performance at the expense of
-3D performance.
-.TP
-This option only takes effect when XAA acceleration is enabled.
-.TP
+2D acceleration and video when XAA acceleration is enabled. Decreasing this
+amount leaves more for 3D textures. Increasing it can improve 2D performance
+at the expense of 3D performance.
Default: depends on the resolution, depth, and available video memory. The
driver attempts to allocate space for at 3 screenfuls of pixmaps plus an
HD-sized XV video. The default used for a specific configuration can be found
@@ -145,7 +143,7 @@ the full benefit without triple buffering (see
.B "Option \*qTripleBuffer\*q"
).
Default for i810: The option is not used.
-Default for i830 and above: Disabled.
+Default for i830 and above: Disabled (This option is currently unstable).
.TP
.BI "Option \*qTripleBuffer\*q \*q" boolean \*q
Enable support for triple buffering. This should improve 3D performance at the
@@ -202,5 +200,5 @@ support reworked for XFree86 4.3 by David Dawes and Keith Whitwell. 852GM,
Keith Whitwell. Lid status support added by Alan Hourihane. Textured video
support for 915G and later chips, RandR 1.2 and hardware modesetting added
by Eric Anholt and Keith Packard. EXA and Render acceleration added by Wang
-Zhenyu. TV out support added by Zou Nan Hai and Keith Packard. 965GM support
-added by Wang Zhenyu.
+Zhenyu. TV out support added by Zou Nan Hai and Keith Packard. 965GM, G33,
+Q33, and Q35 support added by Wang Zhenyu.
commit 2b9961eb9ce8734565ecdb01cb11610714d7f610
Author: Eric Anholt <eric@anholt.net>
Date: Mon Jul 2 15:16:33 2007 -0700
Fix reversed LVDS dither enabling logic on GM965.
diff --git a/src/i830_display.c b/src/i830_display.c
index aba86ae..ebde525 100644
--- a/src/i830_display.c
+++ b/src/i830_display.c
@@ -1019,9 +1019,9 @@ i830_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
if (IS_I965G(pI830))
{
if ((lvds & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
- lvds |= LVDS_DITHER_ENABLE;
- else
lvds &= ~LVDS_DITHER_ENABLE;
+ else
+ lvds |= LVDS_DITHER_ENABLE;
}
OUTREG(LVDS, lvds);
commit 3d9ee8b2991ec0da8cc21b8455ff7f00fd0335b5
Author: Eric Anholt <eric@anholt.net>
Date: Mon Jul 2 14:38:28 2007 -0700
Bug #11365: Disable the panel fitter unless it's needed for the chosen mode.
The automatic panel scaling appears to choose bad sampling on some GM965
hardware for 1:1 mapping modes, and there's no real sense in having it on
if we just want 1:1.
diff --git a/src/i830_lvds.c b/src/i830_lvds.c
index d469815..e2c6e3c 100644
--- a/src/i830_lvds.c
+++ b/src/i830_lvds.c
@@ -261,17 +261,23 @@ i830_lvds_mode_set(xf86OutputPtr output, DisplayModePtr mode,
I830CrtcPrivatePtr intel_crtc = output->crtc->driver_private;
CARD32 pfit_control;
- /* The LVDS pin pair will already have been turned on in the
+ /* The LVDS pin pair will already have been turned on in
* i830_crtc_mode_set since it has a large impact on the DPLL settings.
*/
- /* Enable automatic panel scaling so that non-native modes fill the
- * screen. Should be enabled before the pipe is enabled, according to
+ /* Enable automatic panel scaling for non-native modes so that they fill
+ * the screen. Should be enabled before the pipe is enabled, according to
* register description and PRM.
*/
- pfit_control = (PFIT_ENABLE |
- VERT_AUTO_SCALE | HORIZ_AUTO_SCALE |
- VERT_INTERP_BILINEAR | HORIZ_INTERP_BILINEAR);
+ if (mode->HDisplay != adjusted_mode->HDisplay ||
+ mode->VDisplay != adjusted_mode->VDisplay)
+ {
+ pfit_control = PFIT_ENABLE |
+ VERT_AUTO_SCALE | HORIZ_AUTO_SCALE |
+ VERT_INTERP_BILINEAR | HORIZ_INTERP_BILINEAR;
+ } else {
+ pfit_control = 0;
+ }
if (!IS_I965G(pI830)) {
if (dev_priv->panel_wants_dither)
commit 1e2e301348b4168aeed38b3fdc6b0e43d5678a86
Author: Keith Packard <keithp@dulcimer.keithp.com>
Date: Sat Jun 30 12:45:24 2007 -0700
Fix load detection to use border region instead of blanking.
Make sure there is some border area to use by changing how the pipe is
configured, then pick a scanline in the middle of the border for load
detection. This lets the load detect code use an active pipe instead of
requiring an idle one.
diff --git a/src/i830_crt.c b/src/i830_crt.c
index d9f4ee6..6d70f39 100644
--- a/src/i830_crt.c
+++ b/src/i830_crt.c
@@ -201,15 +201,16 @@ i830_crt_detect_load (xf86CrtcPtr crtc,
ScrnInfoPtr pScrn = output->scrn;
I830Ptr pI830 = I830PTR(pScrn);
I830CrtcPrivatePtr i830_crtc = I830CrtcPrivate(crtc);
- I830OutputPrivatePtr intel_output = output->driver_private;
CARD32 save_bclrpat;
CARD32 save_vtotal;
CARD32 vtotal, vactive;
CARD32 vsample;
+ CARD32 vblank, vblank_start, vblank_end;
CARD32 dsl;
CARD8 st00;
int bclrpat_reg, pipeconf_reg, pipe_dsl_reg;
int vtotal_reg;
+ int vblank_reg;
int pipe = i830_crtc->pipe;
int count, detect;
Bool present;
@@ -218,6 +219,7 @@ i830_crt_detect_load (xf86CrtcPtr crtc,
{
bclrpat_reg = BCLRPAT_A;
vtotal_reg = VTOTAL_A;
+ vblank_reg = VBLANK_A;
pipeconf_reg = PIPEACONF;
pipe_dsl_reg = PIPEA_DSL;
}
@@ -225,18 +227,26 @@ i830_crt_detect_load (xf86CrtcPtr crtc,
{
bclrpat_reg = BCLRPAT_B;
vtotal_reg = VTOTAL_B;
+ vblank_reg = VBLANK_B;
pipeconf_reg = PIPEBCONF;
pipe_dsl_reg = PIPEB_DSL;
}
save_bclrpat = INREG(bclrpat_reg);
save_vtotal = INREG(vtotal_reg);
+ vblank = INREG(vblank_reg);
+
+ vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
+ vactive = (save_vtotal & 0x7ff) + 1;
- vtotal = (save_vtotal >> 16) & 0xfff;
- vactive = save_vtotal & 0x7ff;
+ vblank_start = (vblank & 0xfff) + 1;
+ vblank_end = ((vblank >> 16) & 0xfff) + 1;
- /* sample the middle of the blanking interval */
- vsample = ((vtotal - 3) + (vactive)) >> 1;
+ /* sample in the vertical border, selecting the larger one */
+ if (vblank_start - vactive >= vtotal - vblank_end)
+ vsample = (vblank_start + vactive) >> 1;
+ else
+ vsample = (vtotal + vblank_end) >> 1;
/* Set the border color to purple. */
OUTREG(bclrpat_reg, 0x500050);
@@ -271,8 +281,6 @@ i830_crt_detect_load (xf86CrtcPtr crtc,
* the screen
*/
present = detect * 4 > count * 3;
- xf86DrvMsg (pScrn->scrnIndex, X_ERROR, "present: %s (%d of %d) at %ld desired %ld temp %d\n",
- present ? "TRUE" : "FALSE", detect, count, dsl, vsample, intel_output->load_detect_temp);
return present;
}
@@ -341,11 +349,16 @@ i830_crt_detect(xf86OutputPtr output)
Bool connected;
I830OutputPrivatePtr intel_output = output->driver_private;
- if (intel_output->load_detect_temp)
+ if (!crtc->enabled)
{
xf86SetModeCrtc (&mode, INTERLACE_HALVE_V);
xf86CrtcSetMode (crtc, &mode, RR_Rotate_0, 0, 0);
}
+ else if (intel_output->load_detect_temp)
+ {
+ output->funcs->mode_set (output, &crtc->mode, &crtc->mode);
+ output->funcs->commit (output);
+ }
connected = i830_crt_detect_load (crtc, output);
i830ReleaseLoadDetectPipe (output);
@@ -384,6 +397,7 @@ i830_crt_init(ScrnInfoPtr pScrn)
{
xf86OutputPtr output;
I830OutputPrivatePtr i830_output;
+ I830Ptr pI830 = I830PTR(pScrn);
output = xf86OutputCreate (pScrn, &i830_crt_output_funcs, "VGA");
if (!output)
@@ -395,7 +409,11 @@ i830_crt_init(ScrnInfoPtr pScrn)
return;
}
i830_output->type = I830_OUTPUT_ANALOG;
- i830_output->pipe_mask = ((1 << 0) | (1 << 1));
+ /* i830 (almador) cannot place the analog adaptor on pipe B */
+ if (IS_I830(pI830))
+ i830_output->pipe_mask = (1 << 0);
+ else
+ i830_output->pipe_mask = ((1 << 0) | (1 << 1));
i830_output->clone_mask = ((1 << I830_OUTPUT_ANALOG) |
(1 << I830_OUTPUT_DVO_TMDS));
diff --git a/src/i830_display.c b/src/i830_display.c
index 16ef2cc..aba86ae 100644
--- a/src/i830_display.c
+++ b/src/i830_display.c
@@ -1054,6 +1054,14 @@ i830_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
((adjusted_mode->CrtcHSyncEnd - 1) << 16));
OUTREG(vtot_reg, (adjusted_mode->CrtcVDisplay - 1) |
((adjusted_mode->CrtcVTotal - 1) << 16));
+
+ /*
+ * Give us some border at the bottom for load detection
+ */
+ adjusted_mode->CrtcVBlankStart = adjusted_mode->CrtcVSyncStart;
+ if (adjusted_mode->CrtcVBlankEnd - adjusted_mode->CrtcVBlankStart < 3)
+ adjusted_mode->CrtcVBlankStart = adjusted_mode->CrtcVBlankEnd - 3;
+
OUTREG(vblank_reg, (adjusted_mode->CrtcVBlankStart - 1) |
((adjusted_mode->CrtcVBlankEnd - 1) << 16));
OUTREG(vsync_reg, (adjusted_mode->CrtcVSyncStart - 1) |
@@ -1322,7 +1330,7 @@ i830GetLoadDetectPipe(xf86OutputPtr output)
return output->crtc;
for (i = 0; i < xf86_config->num_crtc; i++)
- if (!xf86CrtcInUse (xf86_config->crtc[i]))
+ if (output->possible_crtcs & (1 << i))
break;
if (i == xf86_config->num_crtc)
@@ -1344,9 +1352,10 @@ i830ReleaseLoadDetectPipe(xf86OutputPtr output)
if (intel_output->load_detect_temp)
{
- output->crtc->enabled = FALSE;
+ xf86CrtcPtr crtc = output->crtc;
output->crtc = NULL;
intel_output->load_detect_temp = FALSE;
+ crtc->enabled = xf86CrtcInUse (crtc);
xf86DisableUnusedFunctions(pScrn);
}
}
diff --git a/src/i830_dvo.c b/src/i830_dvo.c
index 2521ee3..cb461d7 100644
--- a/src/i830_dvo.c
+++ b/src/i830_dvo.c
@@ -462,13 +462,13 @@ i830_dvo_init(ScrnInfoPtr pScrn)
"TMDS");
break;
case I830_OUTPUT_DVO_LVDS:
- intel_output->pipe_mask = (1 << 1);
+ intel_output->pipe_mask = ((1 << 0) | (1 << 1));
intel_output->clone_mask = (1 << I830_OUTPUT_DVO_LVDS);
output = xf86OutputCreate(pScrn, &i830_dvo_output_funcs,
"LVDS");
break;
case I830_OUTPUT_DVO_TVOUT:
- intel_output->pipe_mask = (1 << 1);
+ intel_output->pipe_mask = ((1 << 0) | (1 << 1));
intel_output->clone_mask = (1 << I830_OUTPUT_DVO_TVOUT);
output = xf86OutputCreate(pScrn, &i830_dvo_output_funcs,
"TV");
diff --git a/src/i830_tv.c b/src/i830_tv.c
index b95986f..1c818ba 100644
--- a/src/i830_tv.c
+++ b/src/i830_tv.c
@@ -1357,13 +1357,18 @@ i830_tv_detect(xf86OutputPtr output)
crtc = i830GetLoadDetectPipe (output);
if (crtc)
{
- if (intel_output->load_detect_temp)
+ if (!crtc->enabled)
{
/* we only need the pixel clock set correctly here */
mode = reported_modes[0];
xf86SetModeCrtc (&mode, INTERLACE_HALVE_V);
crtc->funcs->mode_set(crtc, &mode, &mode, 0, 0);
}
+ else if (intel_output->load_detect_temp)
+ {
+ output->funcs->mode_set (output, &crtc->mode, &crtc->mode);
+ output->funcs->commit (output);
+ }
i830_tv_detect_type (crtc, output);
i830ReleaseLoadDetectPipe (output);
}
commit 11862c2e1f23b77b56d7bd8b384579b5e3ae377b
Author: Alan Coopersmith <alan.coopersmith@sun.com>
Date: Thu Jun 28 23:31:28 2007 -0700
Add *~ to .gitignore to skip emacs & patch backup files
diff --git a/.gitignore b/.gitignore
index 8109409..410a074 100644
--- a/.gitignore
+++ b/.gitignore
@@ -5,6 +5,7 @@ Makefile.in
*.la
*.lo
*.o
+*~
aclocal.m4
autom4te.cache
compile
commit 6503eb45023d0db9a94cb9d1e14a26af07a6628d
Author: Alan Coopersmith <alan.coopersmith@sun.com>
Date: Thu Jun 28 23:30:35 2007 -0700
Add AM_PROG_CC_C_O to configure.ac
Clears automake-1.10 warning: src/bios_reader/Makefile.am:8: compiling
`bios_dumper.c' with per-target flags requires `AM_PROG_CC_C_O' in
`configure.ac'
diff --git a/configure.ac b/configure.ac
index 51203fe..a39635e 100644
--- a/configure.ac
+++ b/configure.ac
@@ -48,6 +48,7 @@ AM_MAINTAINER_MODE
AC_DISABLE_STATIC
AC_PROG_LIBTOOL
AC_PROG_CC
+AM_PROG_CC_C_O
AC_CHECK_PROG(gen4asm, [intel-gen4asm], yes, no)
AM_CONDITIONAL(HAVE_GEN4ASM, test x$gen4asm = xyes)
commit 5257e36f502676fd6a44bbb8e747d9138ed3bc5c
Author: Keith Packard <keithp@neko.keithp.com>
Date: Thu Jun 28 15:29:52 2007 -0700
Handle dual-channel LVDS on i855.
Just as with i9xx LVDS, the i855 LVDS can operate in dual-channel mode with
a modified P2 divisor value (7 instead of 14). Just using the existing 9xx
code for 855 appears to work fine.
diff --git a/src/i830_display.c b/src/i830_display.c
index f6e99be..16ef2cc 100644
--- a/src/i830_display.c
+++ b/src/i830_display.c
@@ -92,7 +92,7 @@ typedef struct {
#define I8XX_P2_SLOW 4
#define I8XX_P2_FAST 2
#define I8XX_P2_LVDS_SLOW 14
-#define I8XX_P2_LVDS_FAST 14 /* No fast option */
+#define I8XX_P2_LVDS_FAST 7
#define I8XX_P2_SLOW_LIMIT 165000
#define I9XX_DOT_MIN 20000
@@ -311,8 +311,7 @@ i830FindBestPLL(xf86CrtcPtr crtc, int target, int refclk, intel_clock_t *best_cl
const intel_limit_t *limit = intel_limit (crtc);
int err = target;
- if (IS_I9XX(pI830) && i830PipeHasType(crtc, I830_OUTPUT_LVDS) &&
- (INREG(LVDS) & LVDS_PORT_EN) != 0)
+ if (i830PipeHasType(crtc, I830_OUTPUT_LVDS))
{
/* For LVDS, if the panel is on, just rely on its current settings for
* dual-channel. We haven't figured out how to reliably set up
@@ -1006,7 +1005,7 @@ i830_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
/* Set the B0-B3 data pairs corresponding to whether we're going to
* set the DPLLs for dual-channel mode or not.
*/
- if (clock.p2 == 7)
+ if (clock.p2 == I9XX_P2_LVDS_FAST)
lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
else
lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
commit 16bfcb8042519f24b4494fd621814f39949ceeb6
Author: Keith Packard <keithp@neko.keithp.com>
Date: Thu Jun 28 15:27:56 2007 -0700
Decode PLL registers in LVDS mode a bit better in debug code.
LVDS mode changes how the PLL works in fairly dramatic ways; the debug code
wasn't properly accounting for those differences resulting in fairly bogus
debug output.
diff --git a/src/i830_debug.c b/src/i830_debug.c
index bda263c..055ca93 100644
--- a/src/i830_debug.c
+++ b/src/i830_debug.c
@@ -571,39 +571,91 @@ void i830DumpRegs (ScrnInfoPtr pScrn)
{
fp = INREG(pipe == 0 ? FPA0 : FPB0);
dpll = INREG(pipe == 0 ? DPLL_A : DPLL_B);
- switch ((dpll >> 24) & 0x3) {
- case 0:
- p2 = 10;
- break;
- case 1:
- p2 = 5;
- break;
- default:
- p2 = 1;
- xf86DrvMsg (pScrn->scrnIndex, X_WARNING, "p2 out of range\n");
- break;
+ if (IS_I9XX(pI830))
+ {
+ CARD32 lvds = INREG(LVDS);
+ if ((lvds & LVDS_PORT_EN) &&
+ (lvds & LVDS_PIPEB_SELECT) == (pipe << 30))
+ {
+ if ((lvds & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
+ p2 = 7;
+ else
+ p2 = 14;
+ }
+ else
+ {
+ switch ((dpll >> 24) & 0x3) {
+ case 0:
+ p2 = 10;
+ break;
+ case 1:
+ p2 = 5;
+ break;
+ default:
+ p2 = 1;
+ xf86DrvMsg (pScrn->scrnIndex, X_WARNING, "p2 out of range\n");
+ break;
+ }
+ }
+ switch ((dpll >> 16) & 0xff) {
+ case 1:
+ p1 = 1; break;
+ case 2:
+ p1 = 2; break;
+ case 4:
+ p1 = 3; break;
+ case 8:
+ p1 = 4; break;
+ case 16:
+ p1 = 5; break;
+ case 32:
+ p1 = 6; break;
+ case 64:
+ p1 = 7; break;
+ case 128:
+ p1 = 8; break;
+ default:
+ p1 = 1;
+ xf86DrvMsg (pScrn->scrnIndex, X_WARNING, "p1 out of range\n");
+ break;
+ }
}
- switch ((dpll >> 16) & 0xff) {
- case 1:
- p1 = 1; break;
- case 2:
- p1 = 2; break;
- case 4:
- p1 = 3; break;
- case 8:
- p1 = 4; break;
- case 16:
- p1 = 5; break;
- case 32:
- p1 = 6; break;
- case 64:
- p1 = 7; break;
- case 128:
- p1 = 8; break;
- default:
- p1 = 1;
- xf86DrvMsg (pScrn->scrnIndex, X_WARNING, "p1 out of range\n");
- break;
+ else
+ {
+ CARD32 lvds = INREG(LVDS);
+ if (IS_I85X (pI830) &&
+ (lvds & LVDS_PORT_EN) &&
+ (lvds & LVDS_PIPEB_SELECT) == (pipe << 30))
+ {
+ if ((lvds & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
+ p2 = 7;
+ else
+ p2 = 14;
+ switch ((dpll >> 16) & 0x3f) {
+ case 0x01: p1 = 1; break;
+ case 0x02: p1 = 2; break;
+ case 0x04: p1 = 3; break;
+ case 0x08: p1 = 4; break;
+ case 0x10: p1 = 5; break;
+ case 0x20: p1 = 6; break;
+ default:
+ p1 = 1;
+ xf86DrvMsg (pScrn->scrnIndex, X_WARNING, "LVDS P1 0x%x invalid encoding\n",
+ (dpll >> 16) & 0x3f);
+ break;
+ }
+ }
+ else
+ {
+ if (dpll & (1 << 23))
+ p2 = 4;
+ else
+ p2 = 2;
+ if (dpll & PLL_P1_DIVIDE_BY_TWO)
+ p1 = 2;
+ else
+ p1 = ((dpll >> 16) & 0x3f) + 2;
+ }
}
switch ((dpll >> 13) & 0x3) {
case 0:
commit 9675ccb30818bf831ac4c634751ab4bfe35f7bfe
Author: Wang Zhenyu <zhenyu.z.wang@intel.com>
Date: Wed Jun 27 09:23:33 2007 +0800
EXA: fallback mask transform on i965
It needs to fix shader programs which hasn't been done yet.
diff --git a/src/i965_render.c b/src/i965_render.c
index 2ab1a6b..744501a 100644
--- a/src/i965_render.c
+++ b/src/i965_render.c
@@ -429,6 +429,8 @@ i965_prepare_composite(int op, PicturePtr pSrcPicture,
rotation_program = TRUE;
} else {
pI830->transform[1] = pMaskPicture->transform;
+ if (pI830->transform[1])
+ I830FALLBACK("i965 mask transform not implemented!\n");
pI830->scale_units[1][0] = pMask->drawable.width;
pI830->scale_units[1][1] = pMask->drawable.height;
}
commit 7a2300c88ae59f5b7c3ce89d33147e3f0ca23c18
Author: Wang Zhenyu <zhenyu.z.wang@intel.com>
Date: Wed Jun 27 09:19:22 2007 +0800
EXA: don't have to check offscreen size
DDX will check it for EXA_OFFSCREEN_PIXMAPS flag
diff --git a/src/i830_exa.c b/src/i830_exa.c
index 22618dc..fed4067 100644
--- a/src/i830_exa.c
+++ b/src/i830_exa.c
@@ -400,7 +400,7 @@ I830EXAInit(ScreenPtr pScreen)
return FALSE;
}
memset(pI830->EXADriverPtr, 0, sizeof(*pI830->EXADriverPtr));
-
+
pI830->bufferOffset = 0;
pI830->EXADriverPtr->exa_major = 2;
pI830->EXADriverPtr->exa_minor = 1;
@@ -408,21 +408,14 @@ I830EXAInit(ScreenPtr pScreen)
pI830->EXADriverPtr->offScreenBase = pI830->exa_offscreen->offset;
pI830->EXADriverPtr->memorySize = pI830->exa_offscreen->offset +
pI830->exa_offscreen->size;
-
+ pI830->EXADriverPtr->flags = EXA_OFFSCREEN_PIXMAPS;
+
DPRINTF(PFX, "EXA Mem: memoryBase 0x%x, end 0x%x, offscreen base 0x%x, memorySize 0x%x\n",
pI830->EXADriverPtr->memoryBase,
pI830->EXADriverPtr->memoryBase + pI830->EXADriverPtr->memorySize,
pI830->EXADriverPtr->offScreenBase,
pI830->EXADriverPtr->memorySize);
- if(pI830->EXADriverPtr->memorySize >
- pI830->EXADriverPtr->offScreenBase)
- pI830->EXADriverPtr->flags = EXA_OFFSCREEN_PIXMAPS;
- else {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Not enough video RAM for "
- "offscreen memory manager. Xv disabled\n");
- /* disable Xv here... */
- }
/* Limits are described in the BLT engine chapter under Graphics Data Size
* Limitations, and the descriptions of SURFACE_STATE, 3DSTATE_BUFFER_INFO,
commit fff4a3b58fa18ee2ad91f998d190e90b77c051ab
Author: Carl Worth <cworth@cworth.org>
Date: Mon Jun 25 23:15:58 2007 -0700
Use local structures for vs_state, sf_state, and wm_state
diff --git a/src/i965_render.c b/src/i965_render.c
index d79edd1..2ab1a6b 100644
--- a/src/i965_render.c
+++ b/src/i965_render.c
@@ -268,9 +268,9 @@ static struct brw_sampler_state *src_sampler_state, src_sampler_state_local;
static struct brw_sampler_state *mask_sampler_state, mask_sampler_state_local;
static struct brw_sampler_default_color *default_color_state;
-static struct brw_vs_unit_state *vs_state;
-static struct brw_sf_unit_state *sf_state;
-static struct brw_wm_unit_state *wm_state;
+static struct brw_vs_unit_state *vs_state, vs_state_local;
+static struct brw_sf_unit_state *sf_state, sf_state_local;
+static struct brw_wm_unit_state *wm_state, wm_state_local;
static struct brw_cc_unit_state *cc_state, cc_state_local;
static struct brw_cc_viewport *cc_viewport;
@@ -530,9 +530,6 @@ i965_prepare_composite(int op, PicturePtr pSrcPicture,
state_base_offset = ALIGN(state_base_offset, 64);
state_base = (char *)(pI830->FbBase + state_base_offset);
- vs_state = (void *)(state_base + vs_offset);
- sf_state = (void *)(state_base + sf_offset);
- wm_state = (void *)(state_base + wm_offset);
sf_kernel = (void *)(state_base + sf_kernel_offset);
ps_kernel = (void *)(state_base + ps_kernel_offset);
sip_kernel = (void *)(state_base + sip_kernel_offset);
@@ -786,12 +783,16 @@ i965_prepare_composite(int op, PicturePtr pSrcPicture,
}
/* Set up the vertex shader to be disabled (passthrough) */
+ vs_state = &vs_state_local;
memset(vs_state, 0, sizeof(*vs_state));
vs_state->thread4.nr_urb_entries = URB_VS_ENTRIES;
vs_state->thread4.urb_entry_allocation_size = URB_VS_ENTRY_SIZE - 1;
vs_state->vs6.vs_enable = 0;
vs_state->vs6.vert_cache_disable = 1;
+ vs_state = (void *)(state_base + vs_offset);
+ memcpy (vs_state, &vs_state_local, sizeof (vs_state_local));
+
/* Set up the SF kernel to do coord interp: for each attribute,
* calculate dA/dx and dA/dy. Hand these interpolation coefficients
* back to SF which then hands pixels off to WM.
@@ -804,6 +805,7 @@ i965_prepare_composite(int op, PicturePtr pSrcPicture,
else
memcpy(sf_kernel, sf_kernel_static, sizeof (sf_kernel_static));
+ sf_state = &sf_state_local;
memset(sf_state, 0, sizeof(*sf_state));
sf_state->thread0.kernel_start_pointer =
(state_base_offset + sf_kernel_offset) >> 6;
@@ -835,6 +837,9 @@ i965_prepare_composite(int op, PicturePtr pSrcPicture,
sf_state->sf6.dest_org_vbias = 0x8;
sf_state->sf6.dest_org_hbias = 0x8;
+ sf_state = (void *)(state_base + sf_offset);
+ memcpy (sf_state, &sf_state_local, sizeof (sf_state_local));
+
/* Set up the PS kernel (dispatched by WM) */
if (pMask) {
if (pMaskPicture->componentAlpha &&
@@ -856,6 +861,7 @@ i965_prepare_composite(int op, PicturePtr pSrcPicture,
sizeof (ps_kernel_static_nomask));
}
+ wm_state = &wm_state_local;
memset(wm_state, 0, sizeof (*wm_state));
wm_state->thread0.kernel_start_pointer =
(state_base_offset + ps_kernel_offset) >> 6;
@@ -893,6 +899,9 @@ i965_prepare_composite(int op, PicturePtr pSrcPicture,
wm_state->wm5.enable_8_pix = 0;
wm_state->wm5.early_depth_test = 1;
+ wm_state = (void *)(state_base + wm_offset);
+ memcpy (wm_state, &wm_state_local, sizeof (wm_state_local));
+
/* Begin the long sequence of commands needed to set up the 3D
* rendering pipe
*/
commit 0a8a4afd3c59011d6b1f5b39aedfb9bce0e55c48
Author: Carl Worth <cworth@cworth.org>
Date: Mon Jun 25 23:12:23 2007 -0700
Use local structure for src_sampler_state and mask_sampler_state
diff --git a/src/i965_render.c b/src/i965_render.c
index 0882271..d79edd1 100644
--- a/src/i965_render.c
+++ b/src/i965_render.c
@@ -264,8 +264,8 @@ static int urb_cs_start, urb_cs_size;
static struct brw_surface_state *dest_surf_state, dest_surf_state_local;
static struct brw_surface_state *src_surf_state, src_surf_state_local;
static struct brw_surface_state *mask_surf_state, mask_surf_state_local;
-static struct brw_sampler_state *src_sampler_state;
-static struct brw_sampler_state *mask_sampler_state;
+static struct brw_sampler_state *src_sampler_state, src_sampler_state_local;
+static struct brw_sampler_state *mask_sampler_state, mask_sampler_state_local;
static struct brw_sampler_default_color *default_color_state;
static struct brw_vs_unit_state *vs_state;
@@ -539,10 +539,6 @@ i965_prepare_composite(int op, PicturePtr pSrcPicture,
cc_viewport = (void *)(state_base + cc_viewport_offset);
- src_sampler_state = (void *)(state_base + src_sampler_offset);
- if (pMask)
- mask_sampler_state = (void *)(state_base + mask_sampler_offset);
-
binding_table = (void *)(state_base + binding_table_offset);
vb = (void *)(state_base + vb_offset);
@@ -712,6 +708,7 @@ i965_prepare_composite(int op, PicturePtr pSrcPicture,
binding_table[2] = state_base_offset + mask_surf_offset;
/* PS kernel use this sampler */
+ src_sampler_state = &src_sampler_state_local;
memset(src_sampler_state, 0, sizeof(*src_sampler_state));
src_sampler_state->ss0.lod_preclamp = 1; /* GL mode */
switch(pSrcPicture->filter) {
@@ -748,7 +745,11 @@ i965_prepare_composite(int op, PicturePtr pSrcPicture,
}
src_sampler_state->ss3.chroma_key_enable = 0; /* disable chromakey */
+ src_sampler_state = (void *)(state_base + src_sampler_offset);
+ memcpy (src_sampler_state, &src_sampler_state_local, sizeof (src_sampler_state_local));
+
if (pMask) {
+ mask_sampler_state = &mask_sampler_state_local;
memset(mask_sampler_state, 0, sizeof(*mask_sampler_state));
mask_sampler_state->ss0.lod_preclamp = 1; /* GL mode */
switch(pMaskPicture->filter) {
@@ -779,6 +780,9 @@ i965_prepare_composite(int op, PicturePtr pSrcPicture,
mask_sampler_state->ss1.t_wrap_mode = BRW_TEXCOORDMODE_WRAP;
}
mask_sampler_state->ss3.chroma_key_enable = 0; /* disable chromakey */
+
+ mask_sampler_state = (void *)(state_base + mask_sampler_offset);
+ memcpy (mask_sampler_state, &mask_sampler_state_local, sizeof (mask_sampler_state_local));
}
/* Set up the vertex shader to be disabled (passthrough) */
commit 499166a60fcbf16021bd9ec233790ba55803aa44
Author: Carl Worth <cworth@cworth.org>
Date: Mon Jun 25 23:09:17 2007 -0700
Use local structure for mask_surf_state
diff --git a/src/i965_render.c b/src/i965_render.c
index eb74cd5..0882271 100644
--- a/src/i965_render.c
+++ b/src/i965_render.c
@@ -263,7 +263,7 @@ static int urb_cs_start, urb_cs_size;
static struct brw_surface_state *dest_surf_state, dest_surf_state_local;
static struct brw_surface_state *src_surf_state, src_surf_state_local;
-static struct brw_surface_state *mask_surf_state;
+static struct brw_surface_state *mask_surf_state, mask_surf_state_local;
static struct brw_sampler_state *src_sampler_state;
static struct brw_sampler_state *mask_sampler_state;
static struct brw_sampler_default_color *default_color_state;
@@ -539,9 +539,6 @@ i965_prepare_composite(int op, PicturePtr pSrcPicture,
cc_viewport = (void *)(state_base + cc_viewport_offset);
- if (pMask)
- mask_surf_state = (void *)(state_base + mask_surf_offset);
-
src_sampler_state = (void *)(state_base + src_sampler_offset);
if (pMask)
mask_sampler_state = (void *)(state_base + mask_sampler_offset);
@@ -681,6 +678,7 @@ i965_prepare_composite(int op, PicturePtr pSrcPicture,
/* setup mask surface */
if (pMask) {
+ mask_surf_state = &mask_surf_state_local;
memset(mask_surf_state, 0, sizeof(*mask_surf_state));
mask_surf_state->ss0.surface_type = BRW_SURFACE_2D;
mask_surf_state->ss0.surface_format =
@@ -702,6 +700,9 @@ i965_prepare_composite(int op, PicturePtr pSrcPicture,
mask_surf_state->ss2.mip_count = 0;
mask_surf_state->ss2.render_target_rotation = 0;
mask_surf_state->ss3.pitch = mask_pitch - 1;
+
+ mask_surf_state = (void *)(state_base + mask_surf_offset);
+ memcpy (mask_surf_state, &mask_surf_state_local, sizeof (mask_surf_state_local));
}
/* Set up a binding table for our surfaces. Only the PS will use it */
commit a418ef7316808b239884a90c3fe890220bcc0242
Author: Carl Worth <cworth@cworth.org>
Date: Mon Jun 25 23:07:19 2007 -0700
Use local structure for src_surf_state
diff --git a/src/i965_render.c b/src/i965_render.c
index 09a4362..eb74cd5 100644
--- a/src/i965_render.c
+++ b/src/i965_render.c
@@ -262,7 +262,7 @@ static int urb_sf_start, urb_sf_size;
static int urb_cs_start, urb_cs_size;
static struct brw_surface_state *dest_surf_state, dest_surf_state_local;
-static struct brw_surface_state *src_surf_state;
+static struct brw_surface_state *src_surf_state, src_surf_state_local;
static struct brw_surface_state *mask_surf_state;
static struct brw_sampler_state *src_sampler_state;
static struct brw_sampler_state *mask_sampler_state;
@@ -539,7 +539,6 @@ i965_prepare_composite(int op, PicturePtr pSrcPicture,
cc_viewport = (void *)(state_base + cc_viewport_offset);
- src_surf_state = (void *)(state_base + src_surf_offset);
if (pMask)
mask_surf_state = (void *)(state_base + mask_surf_offset);
@@ -655,6 +654,7 @@ i965_prepare_composite(int op, PicturePtr pSrcPicture,
memcpy (dest_surf_state, &dest_surf_state_local, sizeof (dest_surf_state_local));
/* Set up the source surface state buffer */
+ src_surf_state = &src_surf_state_local;
memset(src_surf_state, 0, sizeof(*src_surf_state));
src_surf_state->ss0.surface_type = BRW_SURFACE_2D;
src_surf_state->ss0.surface_format = i965_get_card_format(pSrcPicture);
@@ -676,6 +676,9 @@ i965_prepare_composite(int op, PicturePtr pSrcPicture,
src_surf_state->ss2.render_target_rotation = 0;
src_surf_state->ss3.pitch = src_pitch - 1;
+ src_surf_state = (void *)(state_base + src_surf_offset);
+ memcpy (src_surf_state, &src_surf_state_local, sizeof (src_surf_state_local));
+
/* setup mask surface */
if (pMask) {
memset(mask_surf_state, 0, sizeof(*mask_surf_state));
commit 0e3c0b17826b7b5a21ee2c1d789b084fc167f1ed
Author: Carl Worth <cworth@cworth.org>
Date: Mon Jun 25 23:05:50 2007 -0700
Use local structure for dest_surf_state
diff --git a/src/i965_render.c b/src/i965_render.c
index 71953e7..09a4362 100644
--- a/src/i965_render.c
+++ b/src/i965_render.c
@@ -261,7 +261,7 @@ static int urb_clip_start, urb_clip_size;
static int urb_sf_start, urb_sf_size;
static int urb_cs_start, urb_cs_size;
-static struct brw_surface_state *dest_surf_state;
+static struct brw_surface_state *dest_surf_state, dest_surf_state_local;
static struct brw_surface_state *src_surf_state;
static struct brw_surface_state *mask_surf_state;
static struct brw_sampler_state *src_sampler_state;
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