Re: memory question (hardware)
>
>
>
>---- Original Message ----
>From: soules@gmail.com
>To: debian-user@lists.debian.org
>Subject: Re: memory question (hardware)
>Date: Sat, 5 Jul 2008 16:27:07 -0400
>
>>Latency, risk of failure, sure... also sheer design complexity
>(since you have
>>to solve the geometry of fitting more circuitry in the same space),
>and
>>subsequent complexity of fabrication (since you have to actually
>make
>>those tiny little circuits). There's also heat dissipation, which
>isn't so so
>>bad for memory but is still nontrivial.
>>Using smaller circuit paths means that the control signals wind up
>being
>>effectively "noisier" too (or so I understand), which affects a
>whole slew
>>of things, including memory timings among others.
>>
>>At least this is all what I remember...!
>>
>>On Sat, Jul 5, 2008 at 2:24 PM, Mag Gam <magawake@gmail.com> wrote:
>>>
>>> Thanks for the responses.
>>>
>>> What is the engineering challenge of having more memory in a
>single die? I expect latency would be a issue. Also, as Brad
>mentioned greater risk of failure.
>>>
>>> Any thing else?
>>>
>>>
>>>
>>> On Fri, Jul 4, 2008 at 11:04 AM, <owens@netptc.net> wrote:
>>>>
>>>> >
>>>> >
>>>> >
>>>> >---- Original Message ----
>>>> >From: magawake@gmail.com
>>>> >To: debian-user@lists.debian.org
>>>> >Subject: RE: memory question (hardware)
>>>> >Date: Thu, 3 Jul 2008 01:08:10 -0400
>>>> >
>>>> >>I am curious...
>>>> >>
>>>> >>
>>>> >>When memory is manufactured why does a stick of 4GB memory cost
>2.5
>>>> >times of
>>>> >>2GB memory? Is the manufacturing process that much different to
>>>> >justify the
>>>> >>cost?
>>>>
>>>> Obviously we can't open up the sticks and look at the chips, but
>the
>>>> usual answer is that the 2G used "the older" technology and the
>4G
>>>> used the "newer" technology and the chip vendor is trying to
>recoup
>>>> development costs. As the "newer" technology becomes the "older"
>>>> technology the cost will go down. With Moore's "law" this gives
>the
>>>> chip vendor about 18 months to recoup most of the development
>costs
>>>> and some profit.
>>>> Larry
>>>> >>
The current way to place more memory cells on the same size die is
known as "scaling"-essentially the horizontal and vertical dimensions
are reduced proportionally so that each cell behaves much like it's
predecessor but is smaller. This is essentially the phenomenon that
gave rise to Moore's "law". Unfortunately this can't physically go
on forever. At some point something "breaks"-e.g.
The interconnection lines are so tiny that even a small spec of
particulate causes a "short" or an "open" to such a degree that the
yield (the percentage of good chips on a die) makes fabrication
uneconomical.
The channel length (distance between the two conducting terminals)
becomes so short that the carriers "tunnel" across the channel
essentially causing the transistor to stop behaving as a switch.
The thickness of the dielectric separating the gates from the rest of
the device becomes so small that the gate no longer controls the flow
of carriers.
etc.
Pundits have hypothesized the 'end of the world as we know it' since
at least 1990 but the chip manufacturers have always found a way.
Let's hope they continue for a few more generations.
Larry
>>>>
>>>>
>>>>
>>>
>>
>>
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