Dziwne logi.
Witam, przeglądając logi znalazłem coś takiego:
(...)
^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@
#define DMA_LOADED_ADDR 0x04000000 /* Address has been loaded */
#define DMA_LOADED_NADDR 0x08000000 /* Next address has been loaded */
/* Values describing the burst-size property from the PROM */
#define DMA_BURST1 0x01
#define DMA_BURST2 0x02
#define DMA_BURST4 0x04
#define DMA_BURST8 0x08
#define DMA_BURST16 0x10
#define DMA_BURST32 0x20
#define DMA_BURST64 0x40
#define DMA_BURSTBITS 0x7f
/* Determine highest possible final transfer address given a base */
#define DMA_MAXEND(addr) (0x01000000UL-(((unsigned long)(addr))&0x00ffffffUL))
/* Yes, I hack a lot of elisp in my spare time... */
#define DMA_ERROR_P(regs) ((((regs)->cond_reg) & DMA_HNDL_ERROR))
#define DMA_IRQ_P(regs) ((((regs)->cond_reg) & (DMA_HNDL_INTR |
DMA_HNDL_ERROR)))
#define DMA_WRITE_P(regs) ((((regs)->cond_reg) & DMA_ST_WRITE))
#define DMA_OFF(regs) ((((regs)->cond_reg) &= (~DMA_ENABLE)))
#define DMA_INTSOFF(regs) ((((regs)->cond_reg) &= (~DMA_INT_ENAB)))
#define DMA_INTSON(regs) ((((regs)->cond_reg) |= (DMA_INT_ENAB)))
#define DMA_PUNTFIFO(regs) ((((regs)->cond_reg) |= DMA_FIFO_INV))
#define DMA_SETSTART(regs, addr) ((((regs)->st_addr) = (char *) addr))
#define DMA_BEGINDMA_W(regs) \
((((regs)->cond_reg |= (DMA_ST_WRITE|DMA_ENABLE|DMA_INT_ENAB))))
#define DMA_BEGINDMA_R(regs) \
((((regs)->cond_reg |= ((DMA_ENABLE|DMA_INT_ENAB)&(~DMA_ST_WRITE)))))
/* For certain DMA chips, we need to disable ints upon irq entry
* and turn them back on when we are done. So in any ESP interrupt
* handler you *must* call DMA_IRQ_ENTRY upon entry and DMA_IRQ_EXIT
* when leaving the handler. You have been warned...
*/
#define DMA_IRQ_ENTRY(dma, dregs) do { \
if(DMA_ISBROKEN(dma)) DMA_INTSOFF(dregs); \
} while (0)
/* Reset the friggin' thing... */
#define DMA_RESET(dma) do { \
struct sparc_dma_registers *regs = dma->regs; \
/* Let the current FIFO drain itself */ \
sparc_dma_pause(regs, (DMA_FIFO_ISDRAIN)); \
/* Reset the logic */ \
regs->cond_reg |= (DMA_RST_SCSI); /* assert */ \
__delay(400); /* let the bits set ;) */ \
regs->cond_reg &= ~(DMA_RST_SCSI); /* de-assert */ \
sparc_dma_enable_interrupts(regs); /* Re-enable interrupts */ \
/* Enable FAST transfers if available */ \
if(dma->revision>dvmarev1) regs->cond_reg |= DMA_3CLKS; \
dma->running = 0; \
} while(0)
#endif /* !CONFIG_SUN3 */
#endif /* !(__M68K_DVMA_H) */
^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@
#define _M68K_DELAY_H
#include <asm/param.h>
/*
* Copyright (C) 1994 Hamish Macdonald
*
* Delay routines, using a pre-computed "loops_per_jiffy" value.
*/
static inline void __delay(unsigned long loops)
{
__asm__ __volatile__ ("1: subql #1,%0; jcc 1b"
(...)
I po tym jest restart serwera.
Kernel 2.4.28, z uslug ssh i named. Co to moze byc? Pierwszy raz sie z czyms
takim spotykam.
--
Pozdrawiam,
Mateusz Frankiewicz
specjalista ds. oprogramowania
IMPULS
32-500 Chrzanów, ul Sokoła 16
KONTAKT:
mateusz@frankiewicz.info
GG: 3920200
GSM: 505 461 937
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