Re: Zicntr / Debian/riscv64: rdcycle causing Illegal instruction

[Bo YU <tsu.yubo@gmail.com>]

Hi,
On Thu, Sep 01, 2022 at 01:49:32PM +0200, Mathieu Malaterre wrote:
> Hi all,
>
> On Thu, Sep 1, 2022 at 9:11 AM Mathieu Malaterre <malat@debian.org> wrote:
> > Aurélien,
> >
> > If you still have some time, could you dump more info:
> >
> > ---------- Forwarded message ---------
> >
> > Is it possible to debug and see the $mepc, $mcause and $mtval at the
> > point at which the fault occurs? That might shed some light on the
> > reason for this issue.
>
> Discussing the issue with upstream lead to the following patch (*).
> Important part pasted here:
>
> [...]
> -#elif HWY_ARCH_RVV
> +  // TODO(janwas): the cycle counter and even the timer CSR are no
> longer in the
> +  // base spec and are part of the Zicntr extension, which is not yet ratified
> +  // as of 2022-09
> +#elif HWY_ARCH_RVV && defined(__riscv_zicntr)
>   asm volatile("rdcycle %0" : "=r"(t));
> [...]
>
> Maybe it will make sense to someone (**).
>
> -M
>
> (*) https://github.com/google/highway/commit/1911baef8c8edf58d99fafd53de433d11837f08c.patch

I can confirm the patch that it works on Unmatched boards with 5.18.0-2
kernel. 

Machine Architecture: riscv64
Package: highway
Package-Time: 1467
Source-Version: 1.0.1-2
Space: 196092
Status: successful
Version: 1.0.1-2

--
Regards,
--
  Bo YU

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