Bug#1036739: ITP: gnucap-modelgen-verilog -- Verilog-AMS behavioural modelling for Gnucap

[Felix Salfelder <felix@salfelder.org>]

Package: wnpp
Severity: wishlist
Owner: Felix Salfelder <felix@salfelder.org>
X-Debbugs-Cc: debian-devel@lists.debian.org, felix@salfelder.org

* Package name    : gnucap-modelgen-verilog
  Version         : 20230520-dev
  Upstream Contact: gnucap-devel <gnucap-devel@gnu.org>
* URL             : http://www.gnucap.org/
* License         : GPL
  Programming Lang: C++, Verilog-AMS
  Description     : Verilog-AMS behavioural modelling for Gnucap

This package provides support for Verilog-AMS behavioural models in
Gnucap as well as supplementary plugins.
  Verilog-AMS is a standardised hardware description language suitable for
analog and mixed signal system modelling.
  Gnucap is a general purpose circuit simulator. It performs nonlinear
dc and transient analyses, Fourier analysis, and ac analysis
linearized at an operating point. It is fully interactive and
command driven. It can also be run in batch mode or as a server.

> usefulness/relevance

This package supplements ADMS, the automatic device model synthesizer.
Unlike ADMS, modelgen-verilog uses a programming language for the model
generation instead of XML template driven text substitution. ADMS is
limited to the analog/SPICE subsection of Verilog-AMS, while
modelgen-verilog is designed to support mixed features and post-spice
architectures.

> maintenance

I will maintain this packgage as a pkg-electronics team member.