Bug#446510: ITP: Alliance VLSI CAD Tools

[Aanjhan <aanjhan@tuxmaniac.com>]

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owner 446510 !
retitle 446510 ITP: alliance -- VLSI CAD system
thankyou

* Package name    : alliance
  Version         : 5.0-20070718
  Upstream Author : LIP6, Université Pierre et Marie Curie
  <alliance-users@asim.lip6.fr>
* URL             : http://www-asim.lip6.fr/recherche/alliance/
* License         : GPL
  Description     : Alliance VLSI CAD system

 Alliance is a complete set of free CAD tools and portable libraries for
 VLSI design. Alliance is the result of more than ten years effort
spent at ASIM department
 of LIP6 laboratory of the Pierre et Marie Curie University (Paris VI,
France).
 Alliance has been used for research projects such as the 875 000
transistors
 StaCS superscalar microprocessor and 400 000 transistors IEEE Gigabit HSL
 Router.
 Alliance provides CAD tools covering most of all the digital design flow:
 * VHDL Compilation and Simulation
 * Model checking and formal proof
 * RTL and Logic synthesis
 * Data-Path compilation
 * Macro-cells generation
 * Place and route
 * Layout edition
 * Netlist extraction and verification
 * Design rules checking

Thanks.
Aanjhan
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