A well funded start-up company located in Santa Clara, CA is looking for a Verification Engineer. This is a full-time position
Our client is an international start-up developing an advanced programmable logic architecture that is about to revolutionize the FPGA market. They provide an unprecedented level of logic density and functionality at a fraction of cost. The technology is based on several years of research and optimizations, which yielded new, interconnect architecture, largely outperforming the traditional architectures.
You will be responsible for building an environment to verify results of sophisticated FPGA tools through simulation from scratch. You will develop and own the process and rules needed to accomplish this task on very complex and large designs. This job will require working with design, validation and applications teams as well as third party vendors.
-BSEE, MSEE preferred, with a minimum of 5 yrs of experience in design or development with FPGAs
-Strong knowledge of Verilog and/or VHDL design simulation with ModeSim
-Development experience with at least one of Perl, sh/csh/ksh or tcl
-Strong knowledge of the Unix/Linux environment
If you know someone that would be a good fit, please forward this email to him or her. For more information, send an email to firstname.lastname@example.org.
Principal & Senior Recruiter, BSEE
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