Re: kaffe in sarge
Guilhem Lavaux wrote:
[snip]
> I need an inlined function which does this, according to katomic.h:
>
> /* Atomically store NEWVAL in *MEM if *MEM is equal to OLDVAL.
> Return the old *MEM value anyway. */
>
> where MEM, NEWVAL and OLDVAL are parameters of that function.
>
> If someone feels to do it (but it is not necessary as there are default
> routines in katomic.h), he/she may also implement atomic_increment,
> atomic_decrement using inline asm.
The appended patch is the cumulated result of my kaffe hacking, diffed
against Debian's kaffe-1.1.4.PRECVS9-1. It includes fixes for some minor
types and inefficiencies, and a glibc-style implementation of atomic.h.
Test-built without problems and tested on big-endian mips. The testsuite
for pthreads hangs in some tests, like it did before with PRECVS8.
Thiemo
diff -urpN kaffe-1.1.4.PRECVS9.orig/build-tree/kaffe-1.1.4.PRECVS9/config/mips/atomic.h kaffe-1.1.4.PRECVS9/build-tree/kaffe-1.1.4.PRECVS9/config/mips/atomic.h
--- kaffe-1.1.4.PRECVS9.orig/build-tree/kaffe-1.1.4.PRECVS9/config/mips/atomic.h 1970-01-01 01:00:00.000000000 +0100
+++ kaffe-1.1.4.PRECVS9/build-tree/kaffe-1.1.4.PRECVS9/config/mips/atomic.h 2005-03-23 19:47:27.000000000 +0100
@@ -0,0 +1,542 @@
+/* Copyright (C) 2005 Thiemo Seufer
+ Atomic functions for MIPS
+
+ This file is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version. */
+
+#include <stdint.h>
+#include <sgidefs.h>
+
+typedef int32_t atomic32_t;
+typedef uint32_t uatomic32_t;
+typedef int_fast32_t atomic_fast32_t;
+typedef uint_fast32_t uatomic_fast32_t;
+
+typedef int64_t atomic64_t;
+typedef uint64_t uatomic64_t;
+typedef int_fast64_t atomic_fast64_t;
+typedef uint_fast64_t uatomic_fast64_t;
+
+typedef intptr_t atomicptr_t;
+typedef uintptr_t uatomicptr_t;
+typedef intmax_t atomic_max_t;
+typedef uintmax_t uatomic_max_t;
+
+/*
+ * MIPS does not have byte and halfword forms of load linked and store
+ * conditional. So for MIPS we stub out the 8- and 16-bit forms.
+ */
+#define __arch_compare_and_exchange_bool_8_int(mem, newval, oldval, mb1, mb2) \
+ ({ __builtin_trap (); 0; })
+
+#define __arch_compare_and_exchange_bool_16_int(mem, newval, oldval, mb1, mb2) \
+ ({ __builtin_trap (); 0; })
+
+#define __arch_compare_and_exchange_val_8_int(mem, newval, oldval, mb1, mb2) \
+ ({ __builtin_trap (); 0; })
+
+#define __arch_compare_and_exchange_val_16_int(mem, newval, oldval, mb1, mb2) \
+ ({ __builtin_trap (); 0; })
+
+#ifdef UP
+# define __MB /* nothing */
+#else
+# define __MB " sync\n"
+# define atomic_full_barrier() __asm ("sync" : : : "memory");
+# define atomic_read_barrier() __asm ("sync" : : : "memory");
+# define atomic_write_barrier() __asm ("sync" : : : "memory");
+#endif
+
+/* Compare and exchange. For all of the "xxx" routines, we expect a
+ "__prev" and a "__cmp" variable to be provided by the enclosing scope,
+ in which values are returned. */
+
+#define __arch_compare_and_exchange_xxx_32_int(mem, new, old, mb1, mb2) \
+({ \
+ __asm__ __volatile__ ( \
+ " .set push\n" \
+ " .set mips2\n" \
+ " .set noreorder\n" \
+ mb1 \
+ "1: ll %[__prev],%[__mem]\n" \
+ " bne %[__prev],%[__old],2f\n" \
+ " li %[__cmp],0\n" \
+ " move %[__cmp],%[__new]\n" \
+ " sc %[__cmp],%[__mem]\n" \
+ " beqz %[__cmp],1b\n" \
+ " nop\n" \
+ mb2 \
+ "2:\n" \
+ " .set pop" \
+ : [__prev] "=&r" (__prev), \
+ [__cmp] "=&r" (__cmp) \
+ : [__mem] "R" (*(volatile atomic32_t *)(mem)), \
+ [__old] "r" ((atomic32_t)(old)), \
+ [__new] "r" ((atomic32_t)(new)) \
+ : "memory"); \
+})
+
+#define __arch_compare_and_exchange_xxx_64_int(mem, new, old, mb1, mb2) \
+({ \
+ __asm__ __volatile__ ( \
+ " .set push\n" \
+ " .set mips3\n" \
+ " .set noreorder\n" \
+ mb1 \
+ "1: lld %[__prev],%[__mem]\n" \
+ " bne %[__prev],%[__old],2f\n" \
+ " li %[__cmp],0\n" \
+ " move %[__cmp],%[__new]\n" \
+ " scd %[__cmp],%[__mem]\n" \
+ " beqz %[__cmp],1b\n" \
+ " nop\n" \
+ mb2 \
+ "2:\n" \
+ " .set pop" \
+ : [__prev] "=&r" (__prev), \
+ [__cmp] "=&r" (__cmp) \
+ : [__mem] "R" (*(volatile atomic32_t *)(mem)), \
+ [__old] "r" ((atomic64_t)(old)), \
+ [__new] "r" ((atomic64_t)(new)) \
+ : "memory"); \
+})
+
+/* For all "bool" routines, we return FALSE if exchange successful. */
+
+#define __arch_compare_and_exchange_bool_32_int(mem, new, old, mb1, mb2) \
+({ unsigned long __prev; int __cmp; \
+ __arch_compare_and_exchange_xxx_32_int(mem, new, old, mb1, mb2); \
+ !__cmp; })
+
+#if _MIPS_SIM == _MIPS_SIM_ABI32
+# define __arch_compare_and_exchange_bool_64_int(mem, new, old, mb1, mb2) \
+ ({ __builtin_trap (); 0; })
+#else
+# define __arch_compare_and_exchange_bool_64_int(mem, new, old, mb1, mb2) \
+({ unsigned long __prev; int __cmp; \
+ __arch_compare_and_exchange_xxx_64_int(mem, new, old, mb1, mb2); \
+ !__cmp; })
+#endif
+
+/* For all "val" routines, return the old value whether exchange
+ successful or not. */
+
+#define __arch_compare_and_exchange_val_32_int(mem, new, old, mb1, mb2) \
+({ unsigned long __prev; int __cmp; \
+ __arch_compare_and_exchange_xxx_32_int(mem, new, old, mb1, mb2); \
+ (typeof (*mem))__prev; })
+
+#if _MIPS_SIM == _MIPS_SIM_ABI32
+# define __arch_compare_and_exchange_val_64_int(mem, new, old, mb1, mb2) \
+ ({ __builtin_trap (); 0; })
+#else
+# define __arch_compare_and_exchange_val_64_int(mem, new, old, mb1, mb2) \
+({ unsigned long __prev; int __cmp; \
+ __arch_compare_and_exchange_xxx_64_int(mem, new, old, mb1, mb2); \
+ (typeof (*mem))__prev; })
+#endif
+
+/* Compare and exchange with "acquire" semantics, ie barrier after. */
+
+#define atomic_compare_and_exchange_bool_acq(mem, new, old) \
+ __atomic_bool_bysize (__arch_compare_and_exchange_bool, int, \
+ mem, new, old, "", __MB)
+
+#define atomic_compare_and_exchange_val_acq(mem, new, old) \
+ __atomic_val_bysize (__arch_compare_and_exchange_val, int, \
+ mem, new, old, "", __MB)
+
+/* Compare and exchange with "release" semantics, ie barrier before. */
+
+#define atomic_compare_and_exchange_bool_rel(mem, new, old) \
+ __atomic_bool_bysize (__arch_compare_and_exchange_bool, int, \
+ mem, new, old, __MB, "")
+
+#define atomic_compare_and_exchange_val_rel(mem, new, old) \
+ __atomic_val_bysize (__arch_compare_and_exchange_val, int, \
+ mem, new, old, __MB, "")
+
+
+/* Atomically store value and return the previous value. */
+
+#define __arch_exchange_8_int(mem, value, mb1, mb2) \
+ ({ __builtin_trap (); 0; })
+
+#define __arch_exchange_16_int(mem, value, mb1, mb2) \
+ ({ __builtin_trap (); 0; })
+
+#define __arch_exchange_32_int(mem, value, mb1, mb2) \
+({ \
+ unsigned int __ret, __tmp; \
+ __asm__ __volatile__ ( \
+ " .set push\n" \
+ " .set mips2\n" \
+ " .set noreorder\n" \
+ mb1 \
+ "1: ll %[__ret],%[__mem]\n" \
+ " move %[__tmp],%[__val]\n" \
+ " sc %[__tmp],%[__mem]\n" \
+ " beqz %[__tmp],1b\n" \
+ " nop\n" \
+ mb2 \
+ " .set pop\n" \
+ : [__ret] "=&r" (__ret), \
+ [__tmp] "=&r" (__tmp) \
+ : [__mem] "R" (*mem), \
+ [__val] "r" ((unsigned int)(value)) \
+ : "memory"); \
+ __ret; })
+
+#if _MIPS_SIM == _MIPS_SIM_ABI32
+# define __arch_exchange_64_int(mem, value, mb1, mb2) \
+ ({ __builtin_trap (); 0; })
+#else
+# define __arch_exchange_64_int(mem, value, mb1, mb2) \
+({ \
+ unsigned long __ret, __tmp; \
+ __asm__ __volatile__ ( \
+ " .set push\n" \
+ " .set mips3\n" \
+ " .set noreorder\n" \
+ mb1 \
+ "1: lld %[__ret],%[__mem]\n" \
+ " move %[__tmp],%[__val]\n" \
+ " scd %[__tmp],%[__mem]\n" \
+ " beqz %[__tmp],1b\n" \
+ " nop\n" \
+ mb2 \
+ " .set pop\n" \
+ : [__ret] "=&r" (__ret), \
+ [__tmp] "=&r" (__tmp) \
+ : [__mem] "R" (*mem), \
+ [__val] "r" (value) \
+ : "memory"); \
+ __ret; })
+#endif
+
+#define atomic_exchange_acq(mem, value) \
+ __atomic_val_bysize (__arch_exchange, int, mem, value, "", __MB)
+
+#define atomic_exchange_rel(mem, value) \
+ __atomic_val_bysize (__arch_exchange, int, mem, value, __MB, "")
+
+
+/* Atomically add value and return the previous (unincremented) value. */
+
+#define __arch_exchange_and_add_8_int(mem, value, mb1, mb2) \
+ ({ __builtin_trap (); 0; })
+
+#define __arch_exchange_and_add_16_int(mem, value, mb1, mb2) \
+ ({ __builtin_trap (); 0; })
+
+#define __arch_exchange_and_add_32_int(mem, value, mb1, mb2) \
+({ \
+ unsigned int __ret, __tmp; \
+ __asm__ __volatile__ ( \
+ " .set push\n" \
+ " .set mips2\n" \
+ " .set noreorder\n" \
+ mb1 \
+ "1: ll %[__ret],%[__mem]\n" \
+ " addu %[__tmp],%[__val],%[__ret]\n" \
+ " sc %[__tmp],%[__mem]\n" \
+ " beqz %[__tmp],1b\n" \
+ " nop\n" \
+ mb2 \
+ " .set pop\n" \
+ : [__ret] "=&r" (__ret), \
+ [__tmp] "=&r" (__tmp) \
+ : [__mem] "R" (*mem), \
+ [__val] "r" ((unsigned int)(value)) \
+ : "memory"); \
+ __ret; })
+
+#if _MIPS_SIM == _MIPS_SIM_ABI32
+# define __arch_exchange_and_add_64_int(mem, value, mb1, mb2) \
+ ({ __builtin_trap (); 0; })
+#else
+# define __arch_exchange_and_add_64_int(mem, value, mb1, mb2) \
+({ \
+ unsigned long __ret, __tmp; \
+ __asm__ __volatile__ ( \
+ " .set push\n" \
+ " .set mips3\n" \
+ " .set noreorder\n" \
+ mb1 \
+ "1: lld %[__ret],%[__mem]\n" \
+ " daddu %[__tmp],%[__val],%[__ret]\n" \
+ " scd %[__tmp],%[__mem]\n" \
+ " beqz %[__tmp],1b\n" \
+ " nop\n" \
+ mb2 \
+ " .set pop\n" \
+ : [__ret] "=&r" (__ret), \
+ [__tmp] "=&r" (__tmp) \
+ : [__mem] "R" (*mem), \
+ [__val] "r" ((unsigned long)(value)) \
+ : "memory"); \
+ __ret; })
+#endif
+
+/* ??? Barrier semantics for atomic_exchange_and_add appear to be
+ undefined. Use full barrier for now, as that's safe. */
+#define atomic_exchange_and_add(mem, value) \
+ __atomic_val_bysize (__arch_exchange_and_add, int, mem, value, __MB, __MB)
+
+
+/* Atomically increment value (and return the incremented value). */
+
+#define __arch_increment_8_int(mem, mb1, mb2) \
+ ({ __builtin_trap (); 0; })
+
+#define __arch_increment_16_int(mem, mb1, mb2) \
+ ({ __builtin_trap (); 0; })
+
+#define __arch_increment_32_int(mem, mb1, mb2) \
+({ \
+ unsigned int __ret, __tmp; \
+ __asm__ __volatile__ ( \
+ " .set push\n" \
+ " .set mips2\n" \
+ " .set noreorder\n" \
+ mb1 \
+ "1: ll %[__ret],%[__mem]\n" \
+ " addiu %[__tmp],%[__ret],1\n" \
+ " sc %[__tmp],%[__mem]\n" \
+ " beqz %[__tmp],1b\n" \
+ " addiu %[__ret],%[__ret],1\n" \
+ mb2 \
+ " .set pop\n" \
+ : [__ret] "=&r" (__ret), \
+ [__tmp] "=&r" (__tmp) \
+ : [__mem] "R" (*mem) \
+ : "memory"); \
+ __ret; })
+
+#if _MIPS_SIM == _MIPS_SIM_ABI32
+# define __arch_increment_64_int(mem, mb1, mb2) \
+ ({ __builtin_trap (); 0; })
+#else
+# define __arch_increment_64_int(mem, mb1, mb2) \
+({ \
+ unsigned long __ret, __tmp; \
+ __asm__ __volatile__ ( \
+ " .set push\n" \
+ " .set mips3\n" \
+ " .set noreorder\n" \
+ mb1 \
+ "1: lld %[__ret],%[__mem]\n" \
+ " daddiu %[__tmp],%[__ret],1\n" \
+ " scd %[__tmp],%[__mem]\n" \
+ " beqz %[__tmp],1b\n" \
+ " daddiu %[__ret],%[__ret],1\n" \
+ mb2 \
+ " .set pop\n" \
+ : [__ret] "=&r" (__ret), \
+ [__tmp] "=&r" (__tmp) \
+ : [__mem] "R" (*mem) \
+ : "memory"); \
+ __ret; })
+#endif
+
+/* ??? Barrier semantics for atomic_increment_val appear to be
+ undefined. Use full barrier for now, as that's safe. */
+#define atomic_increment_val(mem) \
+ __atomic_val_bysize (__arch_increment, int, mem, __MB, __MB)
+
+#define atomic_increment(mem) \
+ ({ __atomic_val_bysize (__arch_increment, int, mem, "", ""); (void) 0; })
+
+
+/* Atomically decrement value (and return the decremented value). */
+
+#define __arch_decrement_8_int(mem, mb1, mb2) \
+ ({ __builtin_trap (); 0; })
+
+#define __arch_decrement_16_int(mem, mb1, mb2) \
+ ({ __builtin_trap (); 0; })
+
+#define __arch_decrement_32_int(mem, mb1, mb2) \
+({ \
+ unsigned int __ret, __tmp; \
+ __asm__ __volatile__ ( \
+ " .set push\n" \
+ " .set mips2\n" \
+ " .set noreorder\n" \
+ mb1 \
+ "1: ll %[__ret],%[__mem]\n" \
+ " addiu %[__tmp],%[__ret],-1\n" \
+ " sc %[__tmp],%[__mem]\n" \
+ " beqz %[__tmp],1b\n" \
+ " addiu %[__ret],%[__ret],-1\n" \
+ mb2 \
+ " .set pop\n" \
+ : [__ret] "=&r" (__ret), \
+ [__tmp] "=&r" (__tmp) \
+ : [__mem] "R" (*mem) \
+ : "memory"); \
+ __ret; })
+
+#if _MIPS_SIM == _MIPS_SIM_ABI32
+# define __arch_decrement_64_int(mem, mb1, mb2) \
+ ({ __builtin_trap (); 0; })
+#else
+# define __arch_decrement_64_int(mem, mb1, mb2) \
+({ \
+ unsigned long __ret, __tmp; \
+ __asm__ __volatile__ ( \
+ " .set push\n" \
+ " .set mips3\n" \
+ " .set noreorder\n" \
+ mb1 \
+ "1: lld %[__ret],%[__mem]\n" \
+ " daddiu %[__tmp],%[__ret],-1\n" \
+ " scd %[__tmp],%[__mem]\n" \
+ " beqz %[__tmp],1b\n" \
+ " daddiu %[__ret],%[__ret],-1\n" \
+ mb2 \
+ " .set pop\n" \
+ : [__ret] "=&r" (__ret), \
+ [__tmp] "=&r" (__tmp) \
+ : [__mem] "R" (*mem) \
+ : "memory"); \
+ __ret; })
+#endif
+
+/* ??? Barrier semantics for atomic_decrement_val appear to be
+ undefined. Use full barrier for now, as that's safe. */
+#define atomic_decrement_val(mem) \
+ __atomic_val_bysize (__arch_decrement, int, mem, __MB, __MB)
+
+#define atomic_decrement(mem) \
+ ({ __atomic_val_bysize (__arch_decrement, int, mem, "", ""); (void) 0; })
+
+
+/* Atomically decrement value and return the previous (undecremented) value. */
+
+#define __arch_decrement_if_positive_8_int(mem, mb1, mb2) \
+ ({ __builtin_trap (); 0; })
+
+#define __arch_decrement_if_positive_16_int(mem, mb1, mb2) \
+ ({ __builtin_trap (); 0; })
+
+#define __arch_decrement_if_positive_32_int(mem, mb1, mb2) \
+({ \
+ signed int __ret, __tmp; \
+ __asm__ __volatile__ ( \
+ " .set push\n" \
+ " .set mips2\n" \
+ " .set noreorder\n" \
+ mb1 \
+ "1: ll %[__ret],%[__mem]\n" \
+ " addiu %[__tmp],%[__ret],-1\n" \
+ " bltz %[__tmp],2f\n" \
+ " nop\n" \
+ " sc %[__tmp],%[__mem]\n" \
+ " beqz %[__tmp],1b\n" \
+ " nop\n" \
+ mb2 \
+ "2:\n" \
+ " .set pop\n" \
+ : [__ret] "=&r" (__ret), \
+ [__tmp] "=&r" (__tmp) \
+ : [__mem] "R" (*mem) \
+ : "memory"); \
+ __ret; })
+
+#if _MIPS_SIM == _MIPS_SIM_ABI32
+# define __arch_decrement_if_positive_64_int(mem, mb1, mb2) \
+ ({ __builtin_trap (); 0; })
+#else
+# define __arch_decrement_if_positive_64_int(mem, mb1, mb2) \
+({ \
+ signed long __ret, __tmp; \
+ __asm__ __volatile__ ( \
+ " .set push\n" \
+ " .set mips3\n" \
+ " .set noreorder\n" \
+ mb1 \
+ "1: lld %[__ret],%[__mem]\n" \
+ " daddiu %[__tmp],%[__ret],-1\n" \
+ " bltz %[__tmp],2f\n" \
+ " nop\n" \
+ " scd %[__tmp],%[__mem]\n" \
+ " beqz %[__tmp],1b\n" \
+ " nop\n" \
+ mb2 \
+ "2:\n" \
+ " .set pop\n" \
+ : [__ret] "=&r" (__ret), \
+ [__tmp] "=&r" (__tmp) \
+ : [__mem] "R" (*mem) \
+ : "memory"); \
+ __ret; })
+#endif
+
+#define atomic_decrement_if_positive(mem) \
+ __atomic_val_bysize (__arch_decrement_if_positive, int, mem, "", __MB)
+
+
+/* Atomically set a bit and return its old value. */
+
+#define __arch_bit_test_set_8_int(mem, bit, mb1, mb2) \
+ ({ __builtin_trap (); 0; })
+
+#define __arch_bit_test_set_16_int(mem, bit, mb1, mb2) \
+ ({ __builtin_trap (); 0; })
+
+#define __arch_bit_test_set_32_int(mem, bit, mb1, mb2) \
+({ \
+ unsigned int __ret, __tmp; \
+ __asm__ __volatile__ ( \
+ " .set push\n" \
+ " .set mips2\n" \
+ " .set noreorder\n" \
+ mb1 \
+ "1: ll %[__tmp],%[__mem]\n" \
+ " or %[__ret],%[__tmp],%[__bit]\n" \
+ " sc %[__ret],%[__mem]\n" \
+ " beqz %[__ret],1b\n" \
+ " and %[__ret],%[__tmp],%[__bit]\n" \
+ mb2 \
+ "2:\n" \
+ " .set pop\n" \
+ : [__ret] "=&r" (__ret), \
+ [__tmp] "=&r" (__tmp) \
+ : [__mem] "R" (*mem), \
+ [__bit] "r" (1UL << bit) \
+ : "memory"); \
+ __ret != 0; })
+
+#if _MIPS_SIM == _MIPS_SIM_ABI32
+# define __arch_bit_test_set_64_int(mem, bit, mb1, mb2) \
+ ({ __builtin_trap (); 0; })
+#else
+# define __arch_bit_test_set_64_int(mem, bit, mb1, mb2) \
+({ \
+ unsigned long __ret, __tmp; \
+ __asm__ __volatile__ ( \
+ " .set push\n" \
+ " .set mips3\n" \
+ " .set noreorder\n" \
+ mb1 \
+ "1: lld %[__tmp],%[__mem]\n" \
+ " or %[__ret],%[__tmp],%[__bit]\n" \
+ " scd %[__ret],%[__mem]\n" \
+ " beqz %[__ret],1b\n" \
+ " and %[__ret],%[__tmp],%[__bit]\n" \
+ mb2 \
+ "2:\n" \
+ " .set pop\n" \
+ : [__ret] "=&r" (__ret), \
+ [__tmp] "=&r" (__tmp) \
+ : [__mem] "R" (*mem), \
+ [__bit] "r" (1 << bit) \
+ : "memory"); \
+ __ret; })
+#endif
+
+#define atomic_bit_test_set(mem) \
+ __atomic_val_bysize (__arch_bit_test_set, int, mem, "", __MB)
diff -urpN kaffe-1.1.4.PRECVS9.orig/build-tree/kaffe-1.1.4.PRECVS9/config/mips/atomicity.h kaffe-1.1.4.PRECVS9/build-tree/kaffe-1.1.4.PRECVS9/config/mips/atomicity.h
--- kaffe-1.1.4.PRECVS9.orig/build-tree/kaffe-1.1.4.PRECVS9/config/mips/atomicity.h 2004-07-13 15:52:00.000000000 +0200
+++ kaffe-1.1.4.PRECVS9/build-tree/kaffe-1.1.4.PRECVS9/config/mips/atomicity.h 1970-01-01 01:00:00.000000000 +0100
@@ -1,50 +0,0 @@
-/* Low-level functions for atomic operations. Mips version.
- Copyright (C) 2001, 2002 Free Software Foundation, Inc.
- This file is part of the GNU C Library.
-
- The GNU C Library is free software; you can redistribute it and/or
- modify it under the terms of the GNU Lesser General Public
- License as published by the Free Software Foundation; either
- version 2.1 of the License, or (at your option) any later version.
-
- The GNU C Library is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- Lesser General Public License for more details.
-
- You should have received a copy of the GNU Lesser General Public
- License along with the GNU C Library; if not, write to the Free
- Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
- 02111-1307 USA. */
-
-#ifndef _MIPS_ATOMICITY_H
-#define _MIPS_ATOMICITY_H 1
-
-#include <inttypes.h>
-
-static inline int
-__attribute__ ((unused))
-compare_and_swap (volatile long int *p, long int oldval, long int newval)
-{
- long int ret, temp;
-
- __asm__ __volatile__
- ("1:\n\t"
- ".set push\n\t"
- ".set mips2\n\t"
- "ll %1,%5\n\t"
- "move %0,$0\n\t"
- "bne %1,%3,2f\n\t"
- "move %0,%4\n\t"
- "sc %0,%2\n\t"
- ".set pop\n\t"
- "beqz %0,1b\n"
- "2:\n\t"
- : "=&r" (ret), "=&r" (temp), "=m" (*p)
- : "r" (oldval), "r" (newval), "m" (*p)
- : "memory");
-
- return ret;
-}
-
-#endif /* atomicity.h */
diff -urpN kaffe-1.1.4.PRECVS9.orig/build-tree/kaffe-1.1.4.PRECVS9/config/mips/callKaffeException.h kaffe-1.1.4.PRECVS9/build-tree/kaffe-1.1.4.PRECVS9/config/mips/callKaffeException.h
--- kaffe-1.1.4.PRECVS9.orig/build-tree/kaffe-1.1.4.PRECVS9/config/mips/callKaffeException.h 2003-12-23 18:26:32.000000000 +0100
+++ kaffe-1.1.4.PRECVS9/build-tree/kaffe-1.1.4.PRECVS9/config/mips/callKaffeException.h 2005-03-22 23:06:41.000000000 +0100
@@ -28,12 +28,14 @@ struct Hjava_lang_Throwable;
static inline void callKaffeException(uintp fp,
uintp handler,
struct Hjava_lang_Throwable* eobj) {
- asm volatile(" \n"
- " move $2,%2 \n"
- " move $fp,%0 \n"
- " jr %1 \n"
- " nop \n"
- " " : : "r" (fp), "r" (handler), "r" (eobj) : "$2");
+ asm volatile("\n"
+ " .set push \n"
+ " .set noreorder \n"
+ " move $2,%2 \n"
+ " jr %1 \n"
+ " move $fp,%0 \n"
+ " .set pop \n"
+ : : "r" (fp), "r" (handler), "r" (eobj));
}
#endif /* __mips_callKaffeException_h */
diff -urpN kaffe-1.1.4.PRECVS9.orig/build-tree/kaffe-1.1.4.PRECVS9/config/mips/common.h kaffe-1.1.4.PRECVS9/build-tree/kaffe-1.1.4.PRECVS9/config/mips/common.h
--- kaffe-1.1.4.PRECVS9.orig/build-tree/kaffe-1.1.4.PRECVS9/config/mips/common.h 2005-03-20 21:30:39.000000000 +0100
+++ kaffe-1.1.4.PRECVS9/build-tree/kaffe-1.1.4.PRECVS9/config/mips/common.h 2005-03-23 16:36:05.000000000 +0100
@@ -31,10 +31,10 @@
#endif
#if defined(HAVE_MIPSII_INSTRUCTIONS)
-#include "atomicity.h"
+#include "atomic.h"
#else
-#define "generic/genatomic.h"
+#include "generic/genatomic.h"
#endif /* defined(HAVE_MIPSII_INSTRUCTIONS) */
diff -urpN kaffe-1.1.4.PRECVS9.orig/build-tree/kaffe-1.1.4.PRECVS9/config/mips/jit.h kaffe-1.1.4.PRECVS9/build-tree/kaffe-1.1.4.PRECVS9/config/mips/jit.h
--- kaffe-1.1.4.PRECVS9.orig/build-tree/kaffe-1.1.4.PRECVS9/config/mips/jit.h 2005-03-16 11:30:57.000000000 +0100
+++ kaffe-1.1.4.PRECVS9/build-tree/kaffe-1.1.4.PRECVS9/config/mips/jit.h 2005-03-22 23:06:41.000000000 +0100
@@ -60,10 +60,10 @@ extern void __mipsGetNextFrame(struct _e
/* The layout of this struct is know by inline assembly. */
typedef struct _methodTrampoline {
- unsigned code[5];
+ unsigned code[4];
struct _methods *meth;
void** where;
- unsigned pad[1];
+ unsigned pad[2];
} methodTrampoline;
extern void mips_do_fixup_trampoline(void);
@@ -72,11 +72,10 @@ extern void mips_do_fixup_trampoline(voi
#define FILL_IN_TRAMPOLINE(t,m,w) \
do { \
uint32 pc = (unsigned int)mips_do_fixup_trampoline; \
- (t)->code[0] = 0x001f1021; /* addu $2,$31,$0 */ \
- (t)->code[1] = 0x3c190000 | (pc >> 16); /* lui $25,addr(high) */ \
- (t)->code[2] = 0x37390000 | (pc & 0xffff);/* ori $25,$25,addr(low) */ \
- (t)->code[3] = 0x0320f809; /* jalr $31,$25 */ \
- (t)->code[4] = 0x00000000; /* nop */ \
+ (t)->code[0] = 0x3c190000 | (pc >> 16); /* lui $25,addr(high) */ \
+ (t)->code[1] = 0x37390000 | (pc & 0xffff);/* ori $25,$25,addr(low) */ \
+ (t)->code[2] = 0x0320f809; /* jalr $31,$25 */ \
+ (t)->code[3] = 0x001f1021; /* addu $2,$31,$0 */ \
(t)->meth = (m); \
(t)->where = (w); \
} while (0)
@@ -92,7 +91,7 @@ extern void mips_do_fixup_trampoline(voi
#define RFD (Rfloat|Rdouble)
#define RG (Rglobal|Rnosaveoncall)
-/* Define the register set, bereits an mips angepasst*/
+/* Define the register set, already adapted for MIPS. */
#define REGISTER_SET \
{ /* i0 */ 0, 0, Reserved, 0, 0, 0 }, \
{ /* i1 */ 0, 0, Reserved, 0, 0, 1 }, \
@@ -208,13 +207,13 @@ extern void mips_do_fixup_trampoline(voi
#define LABEL_Lframe(P,V,L) \
{ \
int framesize = FRAMESIZE; \
- assert((framesize & 0xFFFFF000) == 0); \
+ assert((framesize & 0xFFFF0000) == 0); \
*(P) = (*(P) & 0xFFFF0000) | ((-framesize) & 0xFFFF); \
}
#define LABEL_Lnegframe(P,V,L) \
{ \
int framesize = FRAMESIZE; \
- assert((framesize & 0xFFFFF000) == 0); \
+ assert((framesize & 0xFFFF0000) == 0); \
*(P) = (*(P) & 0xFFFF0000) | ((framesize) & 0xFFFF); \
}
#define LABEL_Llong16b(P,V,L) (P)[0]=((P)[0]&0xFFFF0000)|((((V)-4)>>2)&0xFFFF)
diff -urpN kaffe-1.1.4.PRECVS9.orig/build-tree/kaffe-1.1.4.PRECVS9/config/mips/jit3-icode.h kaffe-1.1.4.PRECVS9/build-tree/kaffe-1.1.4.PRECVS9/config/mips/jit3-icode.h
--- kaffe-1.1.4.PRECVS9.orig/build-tree/kaffe-1.1.4.PRECVS9/config/mips/jit3-icode.h 2004-07-11 21:03:03.000000000 +0200
+++ kaffe-1.1.4.PRECVS9/build-tree/kaffe-1.1.4.PRECVS9/config/mips/jit3-icode.h 2005-03-22 23:06:41.000000000 +0100
@@ -1,4 +1,4 @@
-/* mips/jit-icode.h
+/* mips/jit3-icode.h
* Define the instructions which are present on the MIPS.
*
* Copyright (c) 1996 T. J. Wilkinson & Associates, London, UK.
@@ -189,7 +189,7 @@
#define HAVE_add_int_const_rangecheck(v) __intconst_rangecheck(v)
#define HAVE_add_ref_const_rangecheck(v) __intconst_rangecheck(v)
-#define HAVE_sub_int_const_rangecheck(v) ((v) >= -32767 && (v) <= 327678) /*swapped -67,68*/
+#define HAVE_sub_int_const_rangecheck(v) ((v) >= -32767 && (v) <= 32768) /*swapped -67,68*/
#undef HAVE_cmp_int_const_rangecheck
#define HAVE_load_offset_int_rangecheck(v) __intconst_rangecheck(v)
#define HAVE_load_offset_ref_rangecheck(v) __intconst_rangecheck(v) /* new */
diff -urpN kaffe-1.1.4.PRECVS9.orig/build-tree/kaffe-1.1.4.PRECVS9/config/mips/trampolines.S kaffe-1.1.4.PRECVS9/build-tree/kaffe-1.1.4.PRECVS9/config/mips/trampolines.S
--- kaffe-1.1.4.PRECVS9.orig/build-tree/kaffe-1.1.4.PRECVS9/config/mips/trampolines.S 2005-03-16 11:30:57.000000000 +0100
+++ kaffe-1.1.4.PRECVS9/build-tree/kaffe-1.1.4.PRECVS9/config/mips/trampolines.S 2005-03-22 23:10:10.000000000 +0100
@@ -36,7 +36,7 @@ l1: .word C_FUNC_NAME(soft_fixup_trampol
.globl mips_do_fixup_trampoline
.ent mips_do_fixup_trampoline
mips_do_fixup_trampoline:
- addi $sp, $sp, -48
+ addiu $sp, $sp, -48
# needed by the backtracer
sw $31, 0($sp)
sw $2, 0($sp)
@@ -68,7 +68,7 @@ mips_do_fixup_trampoline:
lw $4, 8($sp)
lw $gp, 4($sp)
lw $31, 0($sp)
- addi $sp, $sp, 48
+ addiu $sp, $sp, 48
move $25, $2
jr $2
.end mips_do_fixup_trampoline
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